A 249Mpixel/s HEVC video-decoder chip for Quad Full HD applications

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 56, Issue , 2013, Pages 162-163

  Huang, Chao Tsung ^a   Tikekar, Mehul ^a   Juvekar, Chiraag ^a   Sze, Vivienne ^b   Chandrakasan, Anantha ^a  

^a MASSACHUSETTS INSTITUTE OF TECHNOLOGY   (United States)

^b TEXAS INSTRUMENTS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

HIERARCHICAL CODING STRUCTURES; HIERARCHICAL STRUCTURES; HIGH-EFFICIENCY VIDEO CODING; INTERPOLATION FILTERS; MEMORY OPTIMIZATION; PRIMARY CONTRIBUTION; PROCESSING ENGINE; VIDEO CODING STANDARD;

DYNAMIC RANDOM ACCESS STORAGE; MOTION COMPENSATION; VIDEO STREAMING;

MOTION PICTURE EXPERTS GROUP STANDARDS;

EID: 84876515942     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2013.6487682     Document Type: Conference Paper

References (6)

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