Design technology of stacked NAND-type FeRAM with two-transistor-type memory cell

Electronics and Communications in Japan

Volumn 96, Issue 4, 2013, Pages 41-52

  Sugano, Koichi ^a   Watanabe, Shigeyoshi ^b  

^a Koito Industries Ltd   (Japan)

^b SHONAN INSTITUTE OF TECHNOLOGY   (Japan)

Author keywords

FeRAM; ferroelectric; NAND structure; nonvolatile memory; stacked structure; WL voltage

Indexed keywords

DESIGN METHOD; DESIGN TECHNOLOGIES; FERAM; NAND STRUCTURES; NON-VOLATILE MEMORY; SMALL CELLS; STACKED STRUCTURE; VOLTAGE GENERATORS;

FERROELECTRIC FILMS; FERROELECTRIC MATERIALS; SEMICONDUCTOR STORAGE;

RANDOM ACCESS STORAGE;

EID: 84875320270     PISSN: 19429533     EISSN: 19429541     Source Type: Journal    
DOI: 10.1002/ecj.10428     Document Type: Article

References (15)

1. Sugano K, Watanabe S., Reading method of NAND type 1-transistor FeRAM with pulse input. Trans IEICE Jpn 2008;J91-C: 668-669. (in Japanese)
2. Sugano K, Watanabe S., Design technology of stacked NAND type 1-transistor FeRAM. IEEJ Trans EIS 2010; 130: 226-234. (in Japanese)
3. Aritome S, Takeuchi Y, Sato S, Watanabe H, Shimizu K, Hemink GJ, Shirota R., A novel side-wall transfer-transistor cell (SWATT cell) for multi-level NAND EEPROMs. IEDM Tech Dig, p 275-278, 1995-12.
4. Aritome S, Takeuchi Y, Sato S, Watanabe H, Shimizu K, Hemink GJ, Shirota R., A novel side-wall transfer-transistor cell (SWATT cell) for highly reliable multi-level NAND EEPROMs. IEEE Trans Electron Devices 1997; 44: 145-152.
5. Brewer JE, Gill M., Nonvolatile memory technologies with emphasis on Flash. Wiley Interscience; 2007.
6. Non-volatile memory technology requirements: The long term. In: International Technology Roadmap for Semiconductors, 2003 Edition, p 215.
7. Tanaka T, et al. Symp on VLSI Technology, 2007.
8. Fukuzumi Y, et al. Optimal integration and characteristics of vertical array device for ultra-high density, bit-cost scalable flash memory. IEDM; 2007.
9. Takato H, et al. IEEE Trans Electron Devices 1991; 38: 573-578.
10. Watanabe S, et al. A novel circuit technology with surrounding gate transistors (SGTs) for ultra high density DRAMs. IEEJ J Solid-State Circuits 1995; 30: 960-971.
11. Bowman KA, et al. Impact of die-to-die and within-die parameter variations on the clock frequency and throughput of multi-core processors. IEEE Trans VLSI Syst 2009; 17: 1679-1690.
12. Yasufuku T, et al. Difficulty of power supply voltage scaling in large scale subthreshold logic circuits. IEICE Trans Electron 2010; E93-C: 332-339.
13. Watanabe S, Minami T., Estimation of yield suppression for 1.5 V, 1 Gbit DRAMs caused by threshold voltage variation of MOSFET due to microscopic fluctuation in dopant distributions. IEICE Trans Electron 1994; E77-C: 273-279.
14. Watanabe S., A design method for an optimal redundant circuit for gigabit DRAM with peripheral circuit yield taken into consideration. Trans IEICE Jpn C-II 1999; J82-C-II: 648-650.
15. Tanaka J, Watanabe S., Patent No. 1339239. A semiconductor nonvolatile read dedicated memory device.