FPGA-based Monte Carlo simulation for fault tree analysis

Microelectronics Reliability

Volumn 44, Issue 6, 2004, Pages 1017-1028

  Ejlali, Alireza ^a   Miremadi, Seyed Ghassem ^a  

^a SHARIF UNIVERSITY OF TECHNOLOGY   (Iran)

Author keywords

[No Author keywords available]

Indexed keywords

BENCHMARKING; COMPUTER SIMULATION; FAULT TREE ANALYSIS; MARKOV PROCESSES; MATHEMATICAL MODELS; MONTE CARLO METHODS; PARAMETER ESTIMATION; RELIABILITY THEORY;

PIPELINED DIGITAL CIRCUITS; RELIABILITY PARAMETERS; TIME-TO-FAILURE TREE;

FIELD PROGRAMMABLE GATE ARRAYS;

EID: 2442463433     PISSN: 00262714     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.microrel.2004.01.016     Document Type: Article

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