Fully-parallel LUT-based (2048,1723) LDPC code decoder for FPGA

2012 19th IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2012

Volumn , Issue , 2012, Pages 408-411

  Torres, V ^a   Perez Pascual, A ^a   Sansaloni, T ^a   Valls, J ^a  

^a ITEAM RESEARCH INSTITUTE   (Spain)

Author keywords

[No Author keywords available]

Indexed keywords

AREA SAVINGS; DESIGN VARIABLES; FPGA DEVICES; LDPC CODES; LOOK UP TABLE; LOW-DENSITY PARITY-CHECK (LDPC) CODES; MIN-SUM ALGORITHM; NON-UNIFORM QUANTIZATION;

ALGORITHMS; PARALLEL ARCHITECTURES; TABLE LOOKUP;

FORWARD ERROR CORRECTION;

EID: 84874626887     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICECS.2012.6463663     Document Type: Conference Paper

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