Low-complexity high-speed decoder design for quasi-cyclic LDPC codes

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 15, Issue 1, 2007, Pages 104-114

  Wang, Zhongfeng ^a,b   Cui, Zhiqiang ^b  

^a IEEE   (United States)

^b Oregon State University   (United States)

Author keywords

Error correction codes; Field programmable gate array (FPGA); Low density parity check (LDPC); Parallel processing; Quasi cyclic (QC) codes

Indexed keywords

ERROR CORRECTION CODES; LOW DENSITY PARITY CHECK (LDPC); QUASI CYCLIC (QC) CODES;

CODING ERRORS; ERROR CORRECTION; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); PARALLEL PROCESSING SYSTEMS;

DECODING;

EID: 33847730317     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2007.891098     Document Type: Article

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