A method to construct low delay single error correction codes for protecting data bits only

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 32, Issue 3, 2013, Pages 479-483

  Reviriego, Pedro ^a   Pontarelli, Salvatore ^b   Maestro, Juan Antonio ^a   Ottavi, Marco ^b  

^a UNIVERSIDAD ANTONIO DE NEBRIJA   (Spain)

^b UNIVERSITY OF ROME TOR VERGATA   (Italy)

Author keywords

Double error detection; error correction codes (ECCs); single error correction (SEC); soft errors

Indexed keywords

CIRCUIT DESIGNS; CORRECT ERROR; DATA BITS; DATA BLOCKS; DELAY REDUCTION; ERROR CORRECTION CODES (ECCS); LOW DELAY; MEMORY PROTECTION; MINIMIZING THE NUMBER OF; SEC-DED; SINGLE ERROR CORRECTIONS; SOFT ERROR;

DELAY CIRCUITS; MICROPROCESSOR CHIPS;

ERROR CORRECTION;

EID: 84874613383     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2012.2226585     Document Type: Article

References (12)

1. M. Nicolaidis, "Design for soft error mitigation," IEEE Trans. Device Mater. Reliab., vol. 5, no. 3, pp. 405-418, Sep. 2005. (Pubitemid 43003060)
2. C. L. Chen and M. Y. Hsiao, "Error-correcting codes for semiconductor memory applications: A state-of-the-art review," IBM J. Res. Develop., vol. 28, no. 2, pp. 124-134, 1984. (Pubitemid 14546564)
3. G. C. Cardarilli, M. Ottavi, S. Pontarelli, M. Re, and A. Salsano, "Fault tolerant solid state mass memory for space applications," IEEE Trans. Aerospace Electron. Syst., vol. 41, no. 4, pp. 1353-1372, Oct. 2005. (Pubitemid 43033919)
4. M. Y. Hsiao "A class of optimal minimum odd-weight column SECDED codes," IBM J. Res. Develop., vol. 14, pp. 395-301, Jul. 1970.
5. R. W. Hamming, "Error detecting and error correcting codes," Bell Syst. Tech. J., vol. 29, pp. 147-160, Apr. 1950.
6. V. Gherman, S. Evain, N. Seymour, and Y. Bonhomme, "Generalized parity-check matrices for SEC-DED codes with fixed parity," in Proc. IEEE On-Line Testing Symp., Jul. 2011, pp. 198-20.
7. M. Richter, K. Oberlaender, and M. Goessel, "New linear SEC-DED codes with reduced triple bit error miscorrection probability," in Proc. IEEE On-Line Testing Symp., Jul. 2008, pp. 37-42.
8. A. M. Saleh, J. J. Serrano, and J. H. Patel, "Reliability of scrubbing recovery-techniques for memory systems," IEEE Trans. Reliab., vol. 39, no. 1, pp. 114-122, Apr. 1990.
9. S. Lin and D. J. Costello, Error Control Coding, 2nd ed. Englewood Cliffs, NJ: Prentice-Hall, 2004.
10. M. Y. Hsiao, D. C. Bossen, and R. T. Chien, "Orthogonal latin square codes," IBM J. Res. Develop., vol. 14, no. 4, pp. 390-394, Jul. 1970.
11. G. Li, I. J. Fair, and W. A. Krzymien, "Low-density parity-check codes for space-time wireless transmission," IEEE Trans. Wirel. Commun., vol. 5, no. 2, pp. 312-322, Feb. 2006.
12. J. E. Stine et al., "FreePDK: An open-source variation-aware design kit," in Proc. IEEE Int. Conf. MSE, Jun. 2007, pp. 173-174. (Pubitemid 47432634)