A 60 GHz PLL synthesizer with an injection locked frequency divider using a fast VCO frequency calibration algorithm

Asia-Pacific Microwave Conference Proceedings, APMC

Volumn , Issue , 2012, Pages 646-648

  Shima, Takahiro ^a   Miyanaga, Kenji ^a   Takinami, Koji ^a  

^a PANASONIC CORPORATION   (Japan)

Author keywords

calibration; injection locked frequency divider; locking range; Phase locked loop; synthesizer

Indexed keywords

90-NM CMOS; CALIBRATION ALGORITHM; CALIBRATION PROCESS; INJECTION LOCKED FREQUENCY DIVIDER; INJECTION LOCKED FREQUENCY DIVIDER(ILFD); LOCKING RANGE; PHASE LOCKED LOOP (PLL); PLL SYNTHESIZER; SUBBANDS; SYNTHESIZER; VCO FREQUENCY CALIBRATIONS;

ALGORITHMS; CALIBRATION; PHASE LOCKED LOOPS; VARIABLE FREQUENCY OSCILLATORS;

FREQUENCY DIVIDING CIRCUITS;

EID: 84874409497     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/APMC.2012.6421690     Document Type: Conference Paper

References (5)

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