A 60 GHz CMOS PLL synthesizer using a wideband injection-locked frequency divider with fast calibration technique

Asia-Pacific Microwave Conference Proceedings, APMC

Volumn , Issue , 2011, Pages 1530-1533

  Shima, Takahiro ^a   Sato, Junji ^a   Mizuno, Koichi ^a   Takinami, Koji ^a  

^a PANASONIC CORPORATION   (Japan)

Author keywords

calibration; injection locked frequency divider; locking range; Phase locked loop; push push voltage controlled oscillator; synthesizer

Indexed keywords

60 GHZ BAND; CALIBRATION ALGORITHM; CALIBRATION TECHNIQUES; DRAFT STANDARD; FREE RUNNING FREQUENCY; INJECTION LOCKED FREQUENCY DIVIDER; INJECTION-LOCKED DIVIDER; LOCKING RANGE; MEASURED RESULTS; PLL SYNTHESIZER; PUSH-PUSH; SYNTHESIZER; WIDE-BAND;

ALGORITHMS; CIRCUIT OSCILLATIONS; FREQUENCY DIVIDING CIRCUITS; PHASE LOCKED LOOPS; VARIABLE FREQUENCY OSCILLATORS;

CALIBRATION;

EID: 84860506891     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)

1. H. Hoshino, R. Tachibana, T. Mitomo, N. Ono, Y. Yoshihara and R. Fujimoto, "A 60-GHz Phase-Locked Loop with Inductor-less Prescaler in 90-nm CMOS," in Proc. IEEE Europian Solid-State Circuits Conference (ESSCIRC), pp. 472-475, September 2007.
2. S. Pellerano, R. Mukhopadhyay, A. Ravi, J. Laskar and Y. Palaskas, "A 39.1-to-41.6GHz äó Fractional-N Frequency Synthesizer in 90nm CMOS," in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, pp. 484-485, February 2008.
3. K. Scheir, G. Vandersteen, Y. Rolain, and P. Wambacq, "A 57-to-66GHz Quadrature PLL in 45nm Digital CMOS," in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, pp. 494-495, February 2009.
4. A. Mirzaei, M. E. Heidari, R. Bagheri and A. Abidi, "Multi-Phase Injection Widens Lock Range of Ring-Oscillator-Based Frequency Dividers," IEEE Journal of Solid-State Circuits, pp. 656-671, March 2009.