A partially reconfigurable architecture supporting hardware threads

FPT 2012 - 2012 International Conference on Field-Programmable Technology

Volumn , Issue , 2012, Pages 269-276

  Wang, Ying ^a   Yan, Jian ^a   Zhou, Xuegong ^a   Wang, Lingli ^a   Luk, Wayne ^b   Peng, Chenglian ^a   Tong, Jiarong ^a  

^a FUDAN UNIVERSITY   (China)

^b IMPERIAL COLLEGE LONDON   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTING PLATFORM; GRAPHICS PROCESSING UNIT; HARDWARE EFFICIENCY; HARDWARE THREADS; HIGH THROUGHPUT; MULTITHREADED; PARTIALLY RECONFIGURABLE ARCHITECTURES; PIPELINE PARALLELISMS; POWER EFFICIENCY; RECONFIGURABLE SYSTEMS; SOFTWARE/HARDWARE; STREAM PROCESSING;

COMPUTER GRAPHICS; EFFICIENCY; MICROPROCESSOR CHIPS; PROGRAM PROCESSORS; RECONFIGURABLE ARCHITECTURES;

HARDWARE;

EID: 84874061865     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/FPT.2012.6412147     Document Type: Conference Paper

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