A predictor-based power-saving policy for DRAM memories

Proceedings - 15th Euromicro Conference on Digital System Design, DSD 2012

Volumn , Issue , 2012, Pages 882-889

  Thomas, Gervin ^a   Chandrasekar, Karthik ^b   Åkesson, Benny ^c   Juurlink, Ben ^a   Goossens, Kees ^c  

^a TECHNISCHE UNIVERSITÄT BERLIN   (Germany)

^b DELFT UNIVERSITY OF TECHNOLOGY   (Netherlands)

^c EINDHOVEN UNIVERSITY OF TECHNOLOGY   (Netherlands)

Author keywords

DRAM Memory; Power Down; Predictor; Predictor based Power Saving Policy; Self Refresh

Indexed keywords

DRAM-MEMORY; POWER SAVINGS; POWER-DOWN; PREDICTOR; SELF-REFRESH;

ENERGY POLICY; ENERGY UTILIZATION; SYSTEMS ANALYSIS;

DYNAMIC RANDOM ACCESS STORAGE;

EID: 84872962085     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DSD.2012.11     Document Type: Conference Paper

References (23)

1. M. Awasthi, D. W. Nellans, R. Balasubramonian, and A. Davis. Prediction Based DRAM Row-Buffer Management in the Many-Core Era. In Proc. 20th International Conference on Parallel Architecture and Compilation Techniques (PACT), pages 183-184, Galveston Island, Texas, October 2011. Poster Track.
2. D. Burger and T. M. Austin. The SimpleScalar tool set, version 2.0. ACM SIGARCH Comput. Archit. News, 25:13-25, June 1997.
3. R. Can, F. Koch, I. Choi, I. Suh, H. Byun, and P. Blumstengel. Save power and improve efficiency in virtualized environment of datacenter by right choice of memory. Technical report, Microsoft Technology Center & Samsung Semiconductor, 2011.
4. K. Chandrasekar, B. Åkesson, and K. Goossens. Improved Power Modeling of DDR SDRAMs. In 14th Euromicro Conference on Digital System Design Architectures, Methods and Tools (DSD), pages 99-108, 2011.
5. K. Chandrasekar et al. DRAMPower: Open Source DRAM Power & Energy Estimation Tool. www.es.ele.tue.nl/drampower, 2012.
6. V. Delaluz, M. Kandemir, N. Vijaykrishnan, A. Sivasubramaniam, and M. J. Irwin. Hardware and software techniques for controlling DRAM power modes. IEEE Transaction on Computers, 50(11):1154-1173, 2001.
7. JEDEC SST Association. DDR3 SDRAM Standard, 2010. JESD79-3E.
8. Y. Joo, Y. Choi, and H. Shim. Energy exploration and reduction of SDRAM memory systems. In Proc. 39th Design Automation Conf, pages 892-897, 2002.
9. C. Lee, M. Potkonjak, and W. H. Mangione-Smith. MediaBench: a tool for evaluating and synthesizing multimedia and communicatons systems. In Proc. 30th ACM/IEEE International symposium on Microarchitecture, MICRO 30, pages 330-335, Washington, DC, USA, 1997. IEEE Computer Society.
10. J. Lee, C. Park, and S. Ha. Memory access pattern analysis and stream cache design for multimedia applications. In Proc. Asia and South Pacific Design Automation Conf the ASP-DAC 2003, pages 22-27, 2003.
11. C. Ma and S. Chen. A DRAM Precharge Policy Based on Address Analysis. In 10th Euromicro Conference on Digital System Design Architectures, Methods and Tools (DSD), pages 244-248, 2007.
12. Micron Technology Inc. DDR3 SDRAM 1Gb Data Sheet, 2006.
13. L. Minas and B. Ellison. Energy Efficiency for Information Technology: How to Reduce Power Consumption in Servers and Data Centers. Intel Press, 2009.
14. U. Y. Ogras and R. Marculescu. Prediction-based Flow Control for Network-on-Chip Traffic. In Proc. 43rd Design Automation Conference, DAC '06, pages 839-844, New York, NY, USA, 2006.
15. S.-I. Park and I.-C. Park. History-based memory mode prediction for improving memory performance. In Proc. Int. Symp. Circuits and Systems ISCAS '03, volume 5, 2003.
16. M. Pedram. Power optimization and management in embedded systems. In Proc. Asia and South Pacific Design Automation Conference, ASPDAC '01, pages 239-244, New York, NY, USA, 2001. ACM.
17. B. Åkesson and K. Goossens. Architectures and modeling of predictable memory controllers for improved system integration. In Proc. Design, Automation, and Test in Europe (DATE), pages 851-856, 2011.
18. B. Åkesson, A. Molnos, A. Hansson, J. Ambrose Angelo, and K. Goossens. Composability and Predictability for Independent Application Development, Verification, and Execution. In M. Hübner and J. Becker, editors, Multiprocessor System-on-Chip - Hardware Design and Tool Integration, chapter 2. Springer, Dec. 2010.
19. V. Stankovic and N. Milenkovic. DRAM Controller with a Complete Predictor: Preliminary Results. In Proc. 7th International Conference on Telecommunications in Modern Satellite, Cable and Broadcasting Services, volume 2, pages 593-596, sept. 2005.
20. G. Thomas, B. Juurlink, and D. Tutsch. Traffic Prediction for NoCs using Fuzzy Logic. In Proc. 2nd International Workshop on New Frontiers in High-performane and Hardware-aware Computing (in Conjunction with HPCA-17), pages 33-40, San Antonio, Texas, USA, February 2011. KIT Scientific Publishing.
21. J. Trajkovic, A. V. Veidenbaum, and A. Kejariwal. Improving SDRAM access energy efficiency for low-power embedded systems. ACM Trans. Embed. Comput. Syst., 7:24:1-24:21, May 2008.
22. O. Vargas. Achieve minimum power consumption in mobile memory subsystems. Technical report, Infineon Technologies AG, 2006.
23. Y. Xu, A. S. Agarwal, and B. T. Davis. Prediction in Dynamic SDRAM Controller Policies. In Proc. 9th International Workshop on Embedded Computer Systems: Architectures, Modeling, and Simulation, SAMOS '09, pages 128-138, Berlin, Heidelberg, 2009. Springer-Verlag.