Application-specific instruction processor for extracting local binary patterns

Conference on Design and Architectures for Signal and Image Processing, DASIP

Volumn , Issue , 2012, Pages 82-89

  Boutellier, Jani ^a   Lundbom, Ismo ^a   Janhunen, Janne ^a   Ylimainen, Jori ^a   Hannuksela, Jari ^a  

^a UNIVERSITY OF OULU   (Finland)

Author keywords

Digital signal processors; Feature extraction; Image texture analysis; Video signal processing

Indexed keywords

APPLICATION-SPECIFIC INSTRUCTION PROCESSORS; CLOCK CYCLES; CLOCK RATE; EMBEDDED DEVICE; FINGERPRINT MATCHING; FPGA BOARDS; HIGH RESOLUTION; IMAGE TEXTURE ANALYSIS; IMPLEMENTATION COMPLEXITY; LOCAL BINARY PATTERNS; LOW-POWER CONSUMPTION; OBJECT DETECTION; PROCESSOR SYNTHESIS; REAL-TIME EXTRACTION; TEXTURE OPERATORS;

CLOCKS; CONTENT BASED RETRIEVAL; DIGITAL SIGNAL PROCESSORS; FACE RECOGNITION; FEATURE EXTRACTION; IMAGE SEGMENTATION; SIGNAL PROCESSING; VIDEO SIGNAL PROCESSING;

APPLICATION SPECIFIC INTEGRATED CIRCUITS;

EID: 84872397244     PISSN: 21649766     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (19)

1. T. Ojala, M. Pietikainen, and T.Maenpaa, "Multiresolution gray-scale and rotation invariant texture classification with local binary patterns," IEEE Transactions on Pattern Analysis and Machine Intelligence, vol. 24, no. 7, pp. 971-987, 2002.
2. M. Heikkila and M. Pietikainen, "A texture-based method for modeling the background and detecting moving objects," IEEE Transactions on Pattern Analysis and Machine Intelligence, vol. 28, no. 4, pp. 657-662, 2006.
3. V. Takala and M. Pietikainen, "Multi-object tracking using color, texture and motion," in IEEE Conference on Computer Vision and Pattern Recognition, Minneapolis, MN, USA, 2007, pp. 1-7.
4. T. Ahonen, A. Hadid, and M. Pietikainen, "Face description with local binary patterns: Application to face recognition," IEEE Transactions on Pattern Analysis and Machine Intelligence, vol. 28, no. 12, pp. 2037-2041, 2006.
5. L. Nanni and A. Lumini, "Local binary patterns for a hybrid fingerprint matcher," Pattern Recognition, vol. 41, no. 11, pp. 3461-3466, 2008.
6. J. Janhunen, P. Salmela, O. Silven, and M. Juntti, "Fixed-versus floating-point implementation of MIMOOFDM detector," in IEEE International Conference on Acoustics, Speech and Signal Processing, Prague, Czech Republic, 2011, pp. 3276-3279.
7. I. Lundbom, "Computing local binary patterns with a transport triggered architecture based microprocessor," M.S. thesis, Department of Electrical Engineering, University of Oulu, 2011.
8. O. Lahdenoja, J. Poikonen, and M. Laiho, "Extracting local binary patterns with MIPA4k vision processor," in 12th International Workshop on Cellular Nanoscale Networks and their Applications, Berkeley, CA, USA, 2010, pp. 1-5.
9. C.-Y. Chang, "Hardware design and implementation of the local binary pattern algorithm," M.S. thesis, Department of Electrical Engineering, National Taiwan Ocean University, 2008.
10. G. Zolynski, T. Braun, and K. Berns, "Local binary pattern based texture analysis in real time using a graphics processing unit," in Robotik 2008, Munich, Germany, 2008, pp. 321-325.
11. T. Maenpaa, The local binary pattern approach to texture analysis-extensions and applications, Ph.D. thesis, University of Oulu, 2003.
12. H. Corporaal, Microprocessor Architectures: From VLIW to TTA, John Wiley & Sons, Inc., New York, NY, USA, 1997.
13. O. Esko, P. Jaaskelainen, P. Huerta, C. S. de La Lama, J. Takala, and J. I. Martinez, "Customized exposed datapath soft-core design flow with compiler support," in 20th International Conference on Field Programmable Logic and Applications, Milano, Italy, 2010, pp. 217-222.
14. S. Jin, D. Kim, T. T. Nguyen, B. Jun, D. Kim, and J. W. Jeon, "An FPGA-based parallel hardware architecture for real-time face detection using a face certainty map," in IEEE International Conference on Application-specific Systems, Architectures and Processors, Boston, MA, USA, 2009, pp. 61-66.
15. W. J. Dally, J. Balfour, D. Black-Shaffer, J. Chen, R. C. Harting, V. Parikh, J. Park, and D. Sheffield, "Efficient embedded computing," Computer, vol. 41, no. 7, pp. 27-32, 2008.
16. M. Muller, "Embedded processing at the heart of life and style," in IEEE International Solid-State Circuits Conference, San Francisco, CA, USA, 2008, pp. 32-37.
17. T. Hiers and M. Webster, "TMS320C6414T/15T/16T power consumption summary, revision A," Tech. Rep., Texas Instruments, 2008.
18. I. Kuon and J. Rose, "Measuring the gap between FPGAs and ASICs," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 26, no. 2, pp. 203-215, 2007.
19. D. G. Chinnery and K. Keutzer, "Closing the power gap between ASIC and custom: an ASIC perspective," in Proceedings of the 42nd annual Design Automation Conference, New York, NY, USA, 2005, pp. 275-280.