Ultra high density logic designs using transistor-level monolithic 3D integration

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD

Volumn , Issue , 2012, Pages 539-546

  Lee, Young Joon ^a   Morrow, Patrick ^b   Lim, Sung Kyu ^a  

^a GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

^b INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER AIDED DESIGN; COMPUTER CIRCUITS; ELECTRIC POWER UTILIZATION; ELECTRONICS PACKAGING; INTEGRATED CIRCUIT DESIGN; INTEGRATED CIRCUIT INTERCONNECTS; LOGIC DESIGN; MONOLITHIC INTEGRATED CIRCUITS;

3-D INTEGRATION; 3D TECHNOLOGY; BENCHMARK CIRCUIT; DESIGN METRICS; LOWER-POWER CONSUMPTION; THROUGH-SILICON-VIA (TSV); TRANSISTOR LEVEL; ULTRAHIGH DENSITY;

THREE DIMENSIONAL INTEGRATED CIRCUITS;

EID: 84872288837     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/2429384.2429500     Document Type: Conference Paper

References (8)

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