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Volumn , Issue , 2010, Pages

Monolithic 3D integration of SRAM and image sensor using two layers of single grain silicon

Author keywords

[No Author keywords available]

Indexed keywords

3-D INTEGRATION; 6T-SRAM; MONOLITHIC INTEGRATION; PHOTODIODE ARRAYS; PIXEL SIZE; READ-OUT CIRCUIT; SENSOR APPLICATIONS; SILICON LAYER; SINGLE GRAINS; STACKED TRANSISTORS; TWO LAYERS;

EID: 79955949068     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/3DIC.2010.5751441     Document Type: Conference Paper
Times cited : (15)

References (8)
  • 1
    • 33747566850 scopus 로고    scopus 로고
    • 3-D ICs: A Novel Chip Design for Improving Deep-Submicrometer Interconnect Performance and Systems-on-Chip Integration
    • MAY
    • K. Banerjee, S. J. Souri, P. Kapur, K. C. Saraswat , 3-D ICs: A Novel Chip Design for Improving Deep-Submicrometer Interconnect Performance and Systems-on-Chip Integration, Proceedings of the IEEE, Vol. 89, NO. 5, MAY 2001
    • (2001) Proceedings of the IEEE , vol.89 , Issue.5
    • Banerjee, K.1    Souri, S.J.2    Kapur, P.3    Saraswat, K.C.4
  • 4
    • 33846070969 scopus 로고    scopus 로고
    • Single-Grain Si TFTs and Circuits Inside Location-Controlled Grains Fabricated Using a Capping Layer of silicon dioxide
    • Jan.
    • V. Rana, R. Ishihara, Y. Hiroshima, S. Inoue, T. Shimoda, W. Metselaar, K. Beenakker, Single-Grain Si TFTs and Circuits Inside Location-Controlled Grains Fabricated Using a Capping Layer of silicon dioxide, IEEE Transactions on Electron Devices, Volume 54, Issue 1, Jan. 2007 Page(s):124-130
    • (2007) IEEE Transactions on Electron Devices , vol.54 , Issue.1 , pp. 124-130
    • Rana, V.1    Ishihara, R.2    Hiroshima, Y.3    Inoue, S.4    Shimoda, T.5    Metselaar, W.6    Beenakker, K.7
  • 7
    • 79955978374 scopus 로고    scopus 로고
    • Monolithic Stacking of Single-Grain Thin-Film Transistors to realize high performance three dimensional integrated circuits
    • M.R Tajari Mofrad, Jaber Derakhshandeh, R. Ishihara and Cees Beenakker, Monolithic Stacking of Single-Grain Thin-Film Transistors to realize high performance three dimensional integrated circuits, Jpn. J. Appl. Phys., 2009.
    • (2009) Jpn. J. Appl. Phys.
    • Tajari Mofrad, M.R.1    Derakhshandeh, J.2    Ishihara, R.3    Beenakker, C.4


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.