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Volumn , Issue , 2012, Pages 283-286

A high-throughput and low-latency interconnection network for multi-core clusters with 3-D stacked L2 tightly-coupled data memory

Author keywords

[No Author keywords available]

Indexed keywords

3-D INTEGRATION; DATA MEMORY; DIGITAL SYSTEM; FABRICATION COST; HIGH-THROUGHPUT; INTERCONNECT LATENCY; LOW-LATENCY; LOW-LATENCY COMMUNICATION; MANY-CORE; MULTI-CORE CLUSTER; PROCESSING CORE; SCALING LIMITATION; STACKING ARCHITECTURE; THREEDIMENSIONAL (3-D); THROUGH SILICON VIAS; TIGHTLY-COUPLED;

EID: 84872181960     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSI-SoC.2012.6379047     Document Type: Conference Paper
Times cited : (7)

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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.