A high-throughput and low-latency interconnection network for multi-core clusters with 3-D stacked L2 tightly-coupled data memory

20th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2012 - Proceedings

Volumn , Issue , 2012, Pages 283-286

  Kang, Kyungsu ^a   Benini, Luca ^b   De Micheli, Giovanni ^a  

^a EPFL   (Switzerland)

^b UNIVERSITY OF BOLOGNA   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

3-D INTEGRATION; DATA MEMORY; DIGITAL SYSTEM; FABRICATION COST; HIGH-THROUGHPUT; INTERCONNECT LATENCY; LOW-LATENCY; LOW-LATENCY COMMUNICATION; MANY-CORE; MULTI-CORE CLUSTER; PROCESSING CORE; SCALING LIMITATION; STACKING ARCHITECTURE; THREEDIMENSIONAL (3-D); THROUGH SILICON VIAS; TIGHTLY-COUPLED;

INTERCONNECTION NETWORKS; MICROPROCESSOR CHIPS; TREES (MATHEMATICS);

MEMORY ARCHITECTURE;

EID: 84872181960     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSI-SoC.2012.6379047     Document Type: Conference Paper

References (17)

1. NVDIA, The next generation CUDA architecture, code named Fermi, [online]. Available: www.nvidia.comlobjectlfermi-architecture.htm.
2. Plurality Ltd. "The hypercore architecture," in white paper, Jan. 2010.
3. ST Microelectronics and CEA, "Platform 2012: A many-core programmable accelerator for ultra-efficient embedded computing in nanometer technology," in white paper, 2010.
4. A. O. Balkan, G. Qu, and U. vishkin, "A mesh-of-trees interconnection network for single-chip parallel processing," ASAP, 2006, pp. 73-80.
5. A. Rahimi et aI., "A fully-synthesizable single-cycle interconnection network for shared-Ll processor clusters," DATE, 2011, pp. 1-6.
6. G. Loh, "3D-stacked memory architectures for multi-core processors," ISCA, 2008, pp. 453-464.
7. J. H. Ahn et aI., "Evaluating the imagine stream architecture," ISCA, 2004, pp. 14-25.
8. S. Kyo, S. Okazaki, and T. Arai, "An integrated memory array processor architecture for embedded image recognition systems," ISCA, 2005, pp. 134-145.
9. U. Kang et aI., "8 Gb 3-D DDR3 DRAM using through-silicon-via technology," IEEE JSSC, vol. 45, no. 1, Jan. 2010.
10. A. Marongiu, M. Ruggiero, and L. Benini, "Efficient OpenMP data mapping for multicore platforms with vertically stacked memory," DATE, 2010, pp. 105-110.
11. E. Gelenbe and G. Pujolle, "Introduction to queueing networks," 2nd Ed., Wiley Publisher, July 1998.
12. Y. Chen et aI., "Cost-effective integration of three-dimensional (3D) ICs emphasizing testing cost analysis," ICCAD, 2010, pp. 471-476.
13. T. Sakurai, "Closed-form expressions for interconnection delay, coupling, and crosstalk in VLSI's," IEEE Trans. Electron Devices, vol. 40, no. 1, pp. 118-124, Jan. 1993.
14. G. Katti et al., "Electrical modeling and characterization of through silicon via for three-dimensional ICs," IEEE Trans. on. Electron Devices, Jan. 2010.
15. Z. Guz et aI., "Many-core vs. many-thread machines: stay away from the valley," IEEE Computer Architecture Letters, vol. 8, no. 1, Jan 2009.
16. ARM Cortex-M3 Processor, [online]. Available: http://www.arm. comlproducts/processors/cortex-mlindex.php
17. D. Tarjan, S. Thoziyoor, and N. P. Jouppi, "CACTI 4.0," HP Laboratories, Palo Alto, CA, Tech. Rep. HPL-2006-86, Jun. 2006.