-
2
-
-
79957574797
-
-
Plurality Ltd. white paper, Jan.
-
Plurality Ltd. "The hypercore architecture," in white paper, Jan. 2010.
-
(2010)
The Hypercore Architecture
-
-
-
4
-
-
34547478190
-
A mesh-of-trees interconnection network for single-chip parallel processing
-
A. O. Balkan, G. Qu, and U. vishkin, "A mesh-of-trees interconnection network for single-chip parallel processing," ASAP, 2006, pp. 73-80.
-
(2006)
ASAP
, pp. 73-80
-
-
Balkan, A.O.1
Qu, G.2
Vishkin, U.3
-
5
-
-
80053505095
-
A fully-synthesizable single-cycle interconnection network for shared-Ll processor clusters
-
A. Rahimi et aI., "A fully-synthesizable single-cycle interconnection network for shared-Ll processor clusters," DATE, 2011, pp. 1-6.
-
(2011)
DATE
, pp. 1-6
-
-
Rahimi, A.1
-
6
-
-
52649125840
-
3D-stacked memory architectures for multi-core processors
-
G. Loh, "3D-stacked memory architectures for multi-core processors," ISCA, 2008, pp. 453-464.
-
(2008)
ISCA
, pp. 453-464
-
-
Loh, G.1
-
7
-
-
4644295630
-
Evaluating the imagine stream architecture
-
J. H. Ahn et aI., "Evaluating the imagine stream architecture," ISCA, 2004, pp. 14-25.
-
(2004)
ISCA
, pp. 14-25
-
-
Ahn, J.H.1
-
8
-
-
27644599162
-
An integrated memory array processor architecture for embedded image recognition systems
-
S. Kyo, S. Okazaki, and T. Arai, "An integrated memory array processor architecture for embedded image recognition systems," ISCA, 2005, pp. 134-145.
-
(2005)
ISCA
, pp. 134-145
-
-
Kyo, S.1
Okazaki, S.2
Arai, T.3
-
9
-
-
73249131982
-
8 Gb 3-D DDR3 DRAM using through-silicon-via technology
-
Jan.
-
U. Kang et aI., "8 Gb 3-D DDR3 DRAM using through-silicon-via technology," IEEE JSSC, vol. 45, no. 1, Jan. 2010.
-
(2010)
IEEE JSSC
, vol.45
, Issue.1
-
-
Kang, U.1
-
10
-
-
77953083551
-
Efficient OpenMP data mapping for multicore platforms with vertically stacked memory
-
A. Marongiu, M. Ruggiero, and L. Benini, "Efficient OpenMP data mapping for multicore platforms with vertically stacked memory," DATE, 2010, pp. 105-110.
-
(2010)
DATE
, pp. 105-110
-
-
Marongiu, A.1
Ruggiero, M.2
Benini, L.3
-
12
-
-
78650872716
-
Cost-effective integration of three-dimensional (3D) ICs emphasizing testing cost analysis
-
Y. Chen et aI., "Cost-effective integration of three-dimensional (3D) ICs emphasizing testing cost analysis," ICCAD, 2010, pp. 471-476.
-
(2010)
ICCAD
, pp. 471-476
-
-
Chen, Y.1
-
13
-
-
0027222295
-
Closed-form expressions for interconnection delay, coupling, and crosstalk in VLSI's
-
Jan.
-
T. Sakurai, "Closed-form expressions for interconnection delay, coupling, and crosstalk in VLSI's," IEEE Trans. Electron Devices, vol. 40, no. 1, pp. 118-124, Jan. 1993.
-
(1993)
IEEE Trans. Electron Devices
, vol.40
, Issue.1
, pp. 118-124
-
-
Sakurai, T.1
-
14
-
-
73349133689
-
Electrical modeling and characterization of through silicon via for three-dimensional ICs
-
Jan.
-
G. Katti et al., "Electrical modeling and characterization of through silicon via for three-dimensional ICs," IEEE Trans. on. Electron Devices, Jan. 2010.
-
(2010)
IEEE Trans. On. Electron Devices
-
-
Katti, G.1
-
15
-
-
67650635164
-
Many-core vs. many-thread machines: Stay away from the valley
-
Jan
-
Z. Guz et aI., "Many-core vs. many-thread machines: stay away from the valley," IEEE Computer Architecture Letters, vol. 8, no. 1, Jan 2009.
-
(2009)
IEEE Computer Architecture Letters
, vol.8
, Issue.1
-
-
Guz, Z.1
-
17
-
-
34547664408
-
-
HP Laboratories, Palo Alto, CA, Tech. Rep. HPL-2006-86, Jun.
-
D. Tarjan, S. Thoziyoor, and N. P. Jouppi, "CACTI 4.0," HP Laboratories, Palo Alto, CA, Tech. Rep. HPL-2006-86, Jun. 2006.
-
(2006)
CACTI 4.0
-
-
Tarjan, D.1
Thoziyoor, S.2
Jouppi, N.P.3
|