Exploiting multi-level scratchpad memories for time-predictable multicore computing

Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors

Volumn , Issue , 2012, Pages 61-66

  Liu, Yu ^a   Zhang, Wei ^b  

^a Southern Illinois University at Carbondale   (United States)

^b Virginia Commonwealth University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALLOCATION METHODS; DYNAMIC MEMORY; L2 CACHE; MEMORY DESIGN; MULTI-CORE COMPUTING; MULTI-CORE PROCESSOR; PROPOSED ARCHITECTURES; SCRATCH PAD MEMORY; TIME PREDICTABILITIES;

DESIGN; ENERGY EFFICIENCY; MEMORY ARCHITECTURE; MULTIPROCESSING SYSTEMS;

CACHE MEMORY;

EID: 84872069545     PISSN: 10636404     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCD.2012.6378618     Document Type: Conference Paper

References (7)

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