Statistical SPICE analysis of a 0.18μm CMOS digital/analog technology during process development

IEEE International Conference on Microelectronic Test Structures

Volumn , Issue , 2001, Pages 19-23

  Rankin, N S ^a   Ng, C ^a   Ee, L S ^a   Boyland, F ^a   Quek, E ^a   Keung, L Y ^a   Walton, A J ^a   Redford, M ^a  

^a UNIVERSITY OF EDINBURGH   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER AIDED DESIGN; COMPUTER SIMULATION; DIGITAL INTEGRATED CIRCUITS; GATES (TRANSISTOR); LINEAR INTEGRATED CIRCUITS; LOGIC DESIGN; MASKS; MONTE CARLO METHODS; MOSFET DEVICES; PARAMETER ESTIMATION; SEMICONDUCTOR DEVICE TESTING; STATISTICAL PROCESS CONTROL;

CORE LOGIC TECHNOLOGY; DEEP SUBMICRON TECHNOLOGY; PARAMETER EXTRACTION; TECHNOLOGY COMPUTER AIDED DESIGN;

CMOS INTEGRATED CIRCUITS;

EID: 0034871417     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (8)

1. SPICE sensitivity analysis of a bipolar test structure during process development
2. Analysis of mixed-signal manufacturability with statistical technology CAD (TCAD)
3. Rapid and cost effective technology development using TCAD: A case study
4. Statistical modeling based on extensive TCAD simulations: Proposed methodology for extraction of fast/slow models and statistical models
5. Predictive technology characterization, missing links between TCAD and compact modeling
6. Techniques for reducing the reverse short channel effect in sub-0.5 μm CMOS
7. Statistical device models from worst case files and electrical test data