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Volumn , Issue , 2001, Pages 393-396

A flexible datapath generator for physical oriented design

Author keywords

[No Author keywords available]

Indexed keywords

ASIC DESIGN; BUILDING BLOCKES; DATA PATHS; DESIGN EFFORT; HIGH FLEXIBILITY; IP BLOCK; SILICON AREA; THROUGHPUT RATE;

EID: 72849110579     PISSN: 19308833     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (11)

References (11)
  • 3
    • 84893662365 scopus 로고    scopus 로고
    • Reducing cross-coupling among interconnect wires in deep-submicron datapath design
    • June
    • J. Yim, C. Kyung "Reducing Cross-Coupling among Interconnect Wires in Deep-Submicron Datapath Design," Design Automation Conference, IEEE, June 2000
    • (2000) Design Automation Conference,IEEE
    • Yim, J.1    Kyung, C.2
  • 6
    • 0030147024 scopus 로고    scopus 로고
    • Design techniques for silicon compiler implementations of high-speed FIR digital filters
    • May
    • R. A. Hawley, B. C. Wong, T. Lin, J. Laskowski, and H. Samueli "Design Techniques for Silicon Compiler Implementations of High-Speed FIR Digital Filters," Journal of Solid-State Circuits, IEEE, vol. 31, no. 5, pp. 656-666, May 1996
    • (1996) Journal of Solid-State Circuits, IEEE , vol.31 , Issue.5 , pp. 656-666
    • Hawley, R.A.1    Wong, B.C.2    Lin, T.3    Laskowski, J.4    Samueli, H.5


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.