Live demonstration: A scaled-down version of the BrainScaleS wafer-scale neuromorphic system

ISCAS 2012 - 2012 IEEE International Symposium on Circuits and Systems

Volumn , Issue , 2012, Pages 702-

  Schemmel, Johannes ^a   Grubl, Andreas ^a   Hartmann, Stephan ^b   Kononov, Alexander ^a   Mayr, Christian ^b   Meier, Karlheinz ^a   Millner, Sebastian ^a   Partzsch, Johannes ^b   Schiefer, Stefan ^b   Scholze, Stefan ^b   Schuffny, Rene ^b   Schwartz, Marc Olivier ^a  

^a UNIVERSITY OF HEIDELBERG   (Germany)

^b DRESDEN UNIVERSITY OF TECHNOLOGY   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

ANALOG PARAMETERS; ANALOG SIGNALS; BIOLOGICAL NEURAL NETWORKS; DEMONSTRATOR SYSTEMS; DIGITAL NETWORKS; FPGA BOARDS; GBIT ETHERNET; HOST-PC; NEUROMORPHIC SYSTEMS; PROGRAMMABLE SYNAPSIS; REAL TIME; SCALED-DOWN VERSIONS; SERIAL LINK; WAFER-SCALE;

NEURAL NETWORKS;

NEURONS;

EID: 84866604579     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCAS.2012.6272131     Document Type: Conference Paper

References (4)

1. J. Schemmel, D. Br̈uderle, A. Gr̈ubl, M. Hock, K. Meier, and S. Millner,"A wafer-scale neuromorphic hardware system for large-scale neural modeling," in Proceedings of the 2010 IEEE International Symposium on Circuits and Systems (ISCAS], 2010, pp. 1947-1950
2. S. Scholze, S. Schiefer, S. Hartmann, J. Partzsch, C. Mayr, S. Ḧoppner, H. Eisenreich, S. Henker, and R. Scḧuffny,"VLSI implementation of a 2. 8GEvent/s packet based AER interface with routing and event sorting functionality," Frontiers in Neuromorphic Engineering, vol. 5, no. 117, pp. 1-13, 2011
3. S. Millner, A. Gr̈ubl, K. Meier, J. Schemmel, and M-O. Schwartz,"A VLSI implementation of the adaptive exponential integrate-and-fire neuron model," in Advances in Neural Information Processing Systems 23, J. Lafferty et al., Eds., 2010, pp. 1642-1650
4. S. Scholze, H. Eisenreich, S. Ḧoppner, G. Ellguth, S. Henker, M. Ander, S. Ḧanzsche, J. Partzsch, C. Mayr, and R. Scḧuffny,"A 32 GBit/s communication SoC for a waferscale neuromorphic system," Integration, the VLSI Journal, 2011, in press