Digitally synthesized stochastic flash ADC using only standard digital cells

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue , 2011, Pages 266-267

  Weaver, Skyler ^a,b   Hershberg, Benjamin ^b   Moon, Un Ku ^b  

^a INTEL CORPORATION   (United States)

^b OREGON STATE UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ANALOG COMPARATORS; CROSS-COUPLINGS; DIGITAL CMOS; FLASH-ADC; GAUSSIANS; INVERSE GAUSSIAN; NAND GATE; ON CHIPS; PIECEWISE-LINEAR; STANDARD DIGITAL CELL; VERILOG CODE;

ANALOG TO DIGITAL CONVERSION; COMPARATORS (OPTICAL); DIGITAL CIRCUITS; DIGITAL LIBRARIES; PIECEWISE LINEAR TECHNIQUES;

VLSI CIRCUITS;

EID: 80052670549     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)

1. T. Sundström and A. Alvandpour, "Utilizing Process Variations for Reference Generation in a Flash ADC," IEEE Trans. Circuits and Systems II, vol. 56, pp. 364-368, May 2009.
2. D. C. Daly and A. P. Chandrakasan, "A 6b 0.2-0.9 V Highly Digital Flash ADC with Comparator Redundancy," in IEEE ISSCC Dig. Tech. Papers, 2008, pp. 554-555.
3. C. Donovan and M. P Flynn, "A 'digital' 6-bit ADC in 0.25-μm CMOS," IEEE J. Solid-State Circuits, vol. 37, no. 3, pp. 432-437, Mar. 2002. (Pubitemid 34307484)
4. S. Weaver, B. Hershberg, P. Kurahashi, D. Knierim, and U. Moon, "Stochastic Flash Analog-to-Digital Conversion," IEEE Trans. Circuits and Systems I, vol. 57, no. 11, pp. 2825-2833, Nov. 2010.