SRAM design in nano-scale CMOS technologies (Invited)

Digest of Technical Papers - Symposium on VLSI Technology

Volumn , Issue , 2012, Pages 85-86

  Zhang, Kevin ^a   Karl, Eric ^a   Wang, Yih ^a  

^a INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CIRCUIT TECHNOLOGY; CMOS TECHNOLOGY; KEY PROCESS; MOORE'S LAW; NANO SCALE; SRAM DESIGN;

CMOS INTEGRATED CIRCUITS;

LOGIC DESIGN;

EID: 84866541256     PISSN: 07431562     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSIT.2012.6242473     Document Type: Conference Paper

References (5)

1. F. Hamzaoglu, et al., "A 153Mb SRAM Design with Dynamic Stability Enhancement and Leakage Reduction in 45nm Hi-K Metal Gate CMOS Technology," ISSCC, pp. 376-377, Feb 2008.
2. E. Karl, et al., "A 4.6GHz, 162Mb Single-Supply SRAM Design in 22nm Tri-Gate CMOS Technology with Active Vmin-Enhancing Assist Circuitry," ISSCC, pp. 230-231, Feb 2012.
3. Y. Wang, et al., "A 4.0 GHz 291Mb Voltage-Scalable SRAM Design in a 32nm High-k + Metal-Gate CMOS Technology with Integrated Power Management," IEEE J. Solid-State Circuits, pp. 148-154, Jan. 2010.
4. K. Zhang, et al, "A 3-GHz 70mb SRAM in 65nm CMOS Technology with Integrated Column-based Dynamic Power Supply," ISSCC, pp. 474-475, Feb 2005.
5. H. Nho, et al., "A 32nm High-k metal gate SRAM with adaptive dynamic stability enhancement for low-voltage operation," ISSCC, pp. 346-347, Feb 2010.