An efficient test design for CMPs cache coherence realizing MESI protocol

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 7373 LNCS, Issue , 2012, Pages 89-98

  Dalui, Mamata ^a   Sikdar, Biplab K ^b  

^a NATIONAL INSTITUTE OF TECHNOLOGY   (India)

^b INDIAN INSTITUTE OF ENGINEERING SCIENCE AND TECHNOLOGY   (India)

Author keywords

Cache coherence; CMP; Coherence controller; Fault detection

Indexed keywords

CACHE COHERENCE; CHIP MULTIPROCESSOR; CMP; DATA COHERENCE; MODELING TOOL; MODULAR STRUCTURES; ON CHIPS; SPECIAL CLASS; TEST DESIGNS;

CACHE MEMORY; CELLULAR AUTOMATA; EMBEDDED SYSTEMS; FAULT DETECTION;

DESIGN;

EID: 84864292307     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/978-3-642-31494-0_11     Document Type: Conference Paper

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