"Smart" design space sampling to predict pare-to-optimal solutions

Proceedings of the ACM SIGPLAN Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES)

Volumn , Issue , 2012, Pages 119-128

  Zuluaga, Marcela ^a   Krause, Andreas ^a   Milder, Peter ^b   Püschel, Markus ^a  

^a ETH ZURICH   (Switzerland)

^b CARNEGIE MELLON UNIVERSITY   (United States)

Author keywords

Area and performance estimation; High level synthesis; Machine learning; Pareto optimality

Indexed keywords

COST PERFORMANCE; DESIGN SPACES; FUNCTIONAL BEHAVIORS; GAUSSIAN PROCESSES; HIGH LEVEL SPECIFICATION; HIGH LEVEL SYNTHESIS; LEARNING-BASED APPROACH; PARETO FRONT; PARETO-OPTIMAL DESIGN; PARETO-OPTIMALITY; PERFORMANCE ESTIMATION; PREDICTION PROBLEM; REGISTER TRANSFER LEVEL; REGRESSION MODEL; SAMPLING STRATEGIES; SORTING NETWORK; STOPPING CRITERIA; TRAINING DATA;

DISCRETE FOURIER TRANSFORMS; EMBEDDED SYSTEMS; FORECASTING; LEARNING ALGORITHMS; LEARNING SYSTEMS; OPTIMAL SYSTEMS; PARETO PRINCIPLE; PROGRAM COMPILERS; REGRESSION ANALYSIS;

DESIGN;

EID: 84864153273     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/2248418.2248436     Document Type: Conference Paper

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