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Volumn , Issue , 2012, Pages 346-353

High-k/metal gates in leading edge silicon devices

Author keywords

Advanced Materials; Advanced Processes; FEOL; Transistor Structures

Indexed keywords

ADVANCED MATERIALS; ADVANCED PROCESS; CHIP PROCESS; COMMERCIAL PRODUCTIONS; FEOL; GATE-LAST; LEADING EDGE; MANUFACTURING PROCESS; METAL-GATE; POLYSILICON GATES; SILICON DEVICES; TRANSISTOR STRUCTURE;

EID: 84863914038     PISSN: 10788743     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASMC.2012.6212925     Document Type: Conference Paper
Times cited : (21)

References (9)
  • 1
    • 0036923437 scopus 로고    scopus 로고
    • Novel Locally Strained Channel Technique for High Performance 55nm CMOS
    • K. Ota et al., "Novel Locally Strained Channel Technique for High Performance 55nm CMOS", 2002 IEDM Technical Digest, pp 27-30
    • 2002 IEDM Technical Digest , pp. 27-30
    • Ota, K.1
  • 2
    • 84863942322 scopus 로고    scopus 로고
    • http://panasonic.co.jp/corp/news/official.data/data.dir/en070619-2/ en070619-2.html
  • 3
    • 50249185641 scopus 로고    scopus 로고
    • A 45nm Logic Technology with Highk+Metal Gate Transistors, Strained Silicon, 9 Cu Interconnect Layers, 193nm Dry Patterning, and 100% Pb-free Packaging
    • K. Mistry et al., "A 45nm Logic Technology with Highk+Metal Gate Transistors, Strained Silicon, 9 Cu Interconnect Layers, 193nm Dry Patterning, and 100% Pb-free Packaging", 2007 IEDM Tech. Dig. pp 247-250.
    • 2007 IEDM Tech. Dig. , pp. 247-250
    • Mistry, K.1
  • 4
    • 3543085768 scopus 로고    scopus 로고
    • Growth Mechanism of Epitaxial NiSi2 Layer in the Ni/Ti/Si(001) Contact for Atomically Flat Interfaces
    • Nakatsuka et al., "Growth Mechanism of Epitaxial NiSi2 Layer in the Ni/Ti/Si(001) Contact for Atomically Flat Interfaces", Fourth International Workshop on Junction Technology, 2004, pp. 143-146.
    • Fourth International Workshop on Junction Technology, 2004 , pp. 143-146
    • Nakatsuka1
  • 5
    • 83855163176 scopus 로고    scopus 로고
    • High Performance 32nm Logic Technology Featuring 2nd Generation High-k + Metal Gate Transistors
    • P. Packan et al., "High Performance 32nm Logic Technology Featuring 2nd Generation High-k + Metal Gate Transistors," 2009 IEDM Tech. Dig. pp 659 -662.
    • 2009 IEDM Tech. Dig. , pp. 659-662
    • Packan, P.1
  • 6
    • 84655171117 scopus 로고    scopus 로고
    • Novel Stress-Memorization-Technology (SMT) for High Electron Mobility Enhancement of Gate Last High-k/Metal Gate Devices
    • K-Y Lim et al., "Novel Stress-Memorization-Technology (SMT) for High Electron Mobility Enhancement of Gate Last High-k/Metal Gate Devices", 2010 IEDM Tech. Dig. pp 229-232.
    • 2010 IEDM Tech. Dig. , pp. 229-232
    • Lim, K.-Y.1
  • 7
    • 84860387371 scopus 로고    scopus 로고
    • Modeling of NMOS Performance Gains from Edge Dislocation Stress
    • C.E. Weber et al., "Modeling of NMOS Performance Gains from Edge Dislocation Stress", 2010 IEDM Tech. Dig. pp 801-804.
    • 2010 IEDM Tech. Dig. , pp. 801-804
    • Weber, C.E.1
  • 8
    • 74049085868 scopus 로고    scopus 로고
    • Advanced SOI CMOS Transistor Technologies for High-Performance Microprocessor Applications
    • M. Horstmann et al., "Advanced SOI CMOS Transistor Technologies for High-Performance Microprocessor Applications", CICC09 pp 149-152.
    • CICC09 , pp. 149-152
    • Horstmann, M.1
  • 9
    • 84858122531 scopus 로고    scopus 로고
    • A Manufacturable Dual Channel (Si and SiGe) Highk Metal Gate CMOS Technology with Multiple Oxides for High Performance and Low Power Applications
    • S. Krishnan et al., "A Manufacturable Dual Channel (Si and SiGe) Highk Metal Gate CMOS Technology with Multiple Oxides for High Performance and Low Power Applications", 2011 IEDM Tech. Dig. pp 634-637.
    • 2011 IEDM Tech. Dig. , pp. 634-637
    • Krishnan, S.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.