The 'Test Model-Checking' approach to the verification of formal memory models of multiprocessors

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 1427 LNCS, Issue , 1998, Pages 464-476

  Nalumasu, Ratan ^a   Ghughal, Rajnish ^a   Mokkedem, Abdel ^a   Gopalakrishnan, Ganesh ^a  

^a UNIVERSITY OF UTAH   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER AIDED ANALYSIS;

ASSOCIATED MEMORY; DESIGN MODELS; FORMAL TESTING; ORDERING RULES; PARALLEL MACHINE; SAFETY PROPERTY; SPLIT-TRANSACTION BUS; TEST MODELING;

MODEL CHECKING;

EID: 84863901125     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/bfb0028767     Document Type: Conference Paper

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