A high-performance, low-cost multiprocessor bus for workstations and midrange servers

Hewlett-Packard Journal

Volumn 47, Issue 1, 1996, Pages 18-24

  Bryg, Williamr ^a   Chan, Kennethk ^a   Fiduccia, Nicholass ^a  

^a NONE

Author keywords

[No Author keywords available]

Indexed keywords

BANDWIDTH; COMPUTATIONAL COMPLEXITY; DATA STORAGE EQUIPMENT; INTERFACES (COMPUTER); MULTIPROCESSING SYSTEMS; NETWORK PROTOCOLS; OPTIMIZATION; PIPELINE PROCESSING SYSTEMS;

MEMORY BANDWIDTHS; MIDRANGE SERVERS; MULTIPROCESSOR BUS; RUNWAY BUS; SYMMETRIC MULTIPROCESSING SYSTEMS;

COMPUTER WORKSTATIONS;

EID: 0030084516     PISSN: 00181153     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article

References (1)

1. P. Stenstrom, "A Survey of Cache Coherence Schemes for Multiprocessors," IEEE Computer; Vol. 23, no. 6, June 1990; pp. 12-25.