Bit error rate estimation in SRAM considering temperature fluctuation

Proceedings - International Symposium on Quality Electronic Design, ISQED

Volumn , Issue , 2012, Pages 516-519

  Kagiyama, Yuki ^a   Okumura, Shunsuke ^a   Yanagida, Koji ^a   Yoshimoto, Shusuke ^a   Nakata, Yohei ^a   Izumi, Shintaro ^a   Kawaguchi, Hiroshi ^a   Yoshimoto, Masahiko ^a,b  

^a KOBE UNIVERSITY   (Japan)

^b JAPAN SCIENCE AND TECHNOLOGY AGENCY   (Japan)

Author keywords

bit error rate; SRAM; static noise margin; temperature fluctuation

Indexed keywords

BER ESTIMATION; BIT-ERRORS; CMOS TECHNOLOGY; DATA MISSING; HIGH TEMPERATURE; MONTE CARLO SIMULATION; OPERATING ENVIRONMENT; OPERATING VOLTAGE; READ MARGIN; STATIC NOISE MARGIN; TEMPERATURE FLUCTUATION; TEST CHIPS; WRITE OPERATIONS;

BIT ERROR RATE; CMOS INTEGRATED CIRCUITS; DISTRIBUTION FUNCTIONS; ESTIMATION; MONTE CARLO METHODS; NORMAL DISTRIBUTION; TEMPERATURE DISTRIBUTION;

STATIC RANDOM ACCESS STORAGE;

EID: 84863652366     PISSN: 19483287     EISSN: 19483295     Source Type: Conference Proceeding    
DOI: 10.1109/ISQED.2012.6187542     Document Type: Conference Paper

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