WCET-aware static locking of instruction caches

Proceedings - International Symposium on Code Generation and Optimization, CGO 2012

Volumn , Issue , 2012, Pages 44-52

  Plazar, Sascha ^a   Kleinsorge, Jan C ^a   Marwedel, Peter ^a   Falk, Heiko ^b  

^a TU DORTMUND UNIVERSITY   (Germany)

^b UNIVERSITY OF ULM   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

ANALYSIS TECHNIQUES; BASIC BLOCKS; CACHE BEHAVIOR; EXECUTION TIME; HARD REAL-TIME SYSTEMS; ILP MODELS; INSTRUCTION CACHES; KEY PARAMETERS; MEMORY BLOCKS; MEMORY SYSTEMS; OPTIMIZATION TECHNIQUES; RUNTIMES; SYSTEM DESIGNERS; TIMING CONSTRAINTS; UPPER BOUND; WORST-CASE EXECUTION; WORST-CASE EXECUTION TIME;

EMBEDDED SYSTEMS; LINEAR PROGRAMMING; NETWORK COMPONENTS; OPTIMIZATION; REAL TIME SYSTEMS; SYSTEMS ANALYSIS; TIMING CIRCUITS;

CACHE MEMORY;

EID: 84863483478     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/2259016.2259023     Document Type: Conference Paper

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