A framework for FPGA acceleration of large graph problems: Graphlet counting case study

2011 International Conference on Field-Programmable Technology, FPT 2011

Volumn , Issue , 2011, Pages

  Betkaoui, Brahim ^a   Thomas, David B ^a   Luk, Wayne ^a   Przulj, Natasa ^a  

^a IMPERIAL COLLEGE LONDON   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

APPLICATION DOMAINS; CLUSTER-BASED; COMPUTING PLATFORM; EXECUTION TIME; GRAPH ALGORITHMS; GRAPH ANALYSIS; GRAPH CLASS; GRAPH DATA; GRAPH PROCESSING; HARDWARE IMPLEMENTATIONS; HARDWARE PERFORMANCE; LARGE GRAPHS; LARGE-SCALE GRAPH PROBLEMS; LATENCY PROBLEM; LOW-LATENCY; MEMORY HIERARCHY; MEMORY LATENCIES; OFF-CHIP MEMORIES; ON CHIPS; PARTITIONING GRAPHS; PROCESS GRAPHS; PROCESSING ELEMENTS; QUANTITATIVE COMPARISON; RECONFIGURABLE ARCHITECTURE; RECONFIGURABLE DEVICES; SCALE-FREE; SHORT-PATH; SOCIAL NETWORKS; SOFTWARE IMPLEMENTATION; SUBGRAPHS;

ALGORITHMS; BIOINFORMATICS; CLUSTER COMPUTING; DATA HANDLING; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); GRAPHIC METHODS; HARDWARE; RANDOM ACCESS STORAGE;

GRAPH THEORY;

EID: 84863405450     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/FPT.2011.6132667     Document Type: Conference Paper

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