Impact of FPGA architecture on resource sharing in high-level synthesis

ACM/SIGDA International Symposium on Field Programmable Gate Arrays - FPGA

Volumn , Issue , 2012, Pages 111-114

  Hadjis, Stefan ^a   Canis, Andrew ^a   Anderson, Jason H ^a   Choi, Jongsok ^a   Nam, Kevin ^a   Brown, Stephen ^a   Czajkowski, Tomasz ^b  

^a UNIVERSITY OF TORONTO   (Canada)

^b Altera Toronto Technology Centre   (Canada)

Author keywords

field programmable gate arrays; FPGAs; high level synthesis; resource sharing

Indexed keywords

BINDING PHASE; CIRCUIT SPECIFICATIONS; FPGA ARCHITECTURES; FUNCTIONAL UNITS; HIGH LEVEL SYNTHESIS; LOGIC ELEMENTS; MULTIPLE OPERATIONS; RESOURCE SHARING;

STORMS;

FIELD PROGRAMMABLE GATE ARRAYS (FPGA);

EID: 84863268242     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/2145694.2145712     Document Type: Conference Paper

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