Real-time FPGA-based multichannel spike sorting using hebbian eigenfilters

IEEE Journal on Emerging and Selected Topics in Circuits and Systems

Volumn 1, Issue 4, 2011, Pages 502-515

  Yu, Bo ^a   Mak, Terrence ^b   Li, Xiangyu ^a   Xia, Fei ^c   Yakovlev, Alexandre ^c   Sun, Yihe ^a   Poon, Chi Sang ^d  

^a TSINGHUA UNIVERSITY   (China)

^b NEWCASTLE UNIVERSITY   (United Kingdom)

^c NEWCASTLE UNIVERSITY   (United Kingdom)

^d MASSACHUSETTS INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

Brain machine interface (BMI); field programmable gate array (FPGAs); hardware architecture design; Hebbian learning; spike sorting

Indexed keywords

BRAIN MACHINE INTERFACE; BROAD APPLICATION; COMPUTATIONAL EFFORT; COMPUTING RESOURCE; COVARIANCE ANALYSIS; EIGENFILTER; EIGENVALUE DECOMPOSITION; FOLDING TECHNIQUE; HARDWARE ARCHITECTURE; HARDWARE ARCHITECTURE DESIGN; HARDWARE DESIGN; HARDWARE SHARING; HEBBIAN; HEBBIAN LEARNING; LOW COST HARDWARE; MULTI-CHANNEL; MULTIPLE CHANNELS; NEUROREHABILITATION; PCA ALGORITHMS; PRINCIPAL COMPONENTS ANALYSIS; SIGNAL RECORDING; SPIKE SORTING ALGORITHMS; SPIKE TRAIN; SPIKE-SORTING;

EIGENVALUES AND EIGENFUNCTIONS; HARDWARE; PROSTHETICS;

PRINCIPAL COMPONENT ANALYSIS;

EID: 84863116446     PISSN: 21563357     EISSN: None     Source Type: Journal    
DOI: 10.1109/JETCAS.2012.2183430     Document Type: Article

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