Power feasibility of implantable digital spike sorting circuits for neural prosthetic systems

IEEE Transactions on Neural Systems and Rehabilitation Engineering

Volumn 13, Issue 3, 2005, Pages 272-279

  Zumsteg, Zachary S ^a,c   Kemere, Caleb ^a,d   O'Driscoll, Stephen ^a,d   Santhanam, Gopal ^a,d   Ahmed, Rizwan E ^b   Shenoy, Krishna V ^a   Meng, Teresa H ^a  

^a Stanford University   (United States)

^b QUALCOMM INC   (United States)

^c UNIVERSITY OF CALIFORNIA   (United States)

^d STANFORD UNIVERSITY   (United States)

Author keywords

Analog to digital converter (ADC); Brain machine interfaces (BMI); Low power; Neural prosthetics; Spike sorting

Indexed keywords

ALGORITHMS; BRAIN; NEUROLOGY; PROSTHETICS; REAL TIME SYSTEMS; SIGNAL PROCESSING;

BRAIN-MACHINE INTERFACES (BMI); LOW-POWER; NEURAL PROSTHETICS; SPIKE SORTING;

DIGITAL CIRCUITS;

METAL OXIDE;

ACTION POTENTIAL; ALGORITHM; ARTICLE; ARTIFICIAL NEURAL NETWORK; CONCEPT FORMATION; DIGITAL SPIKE SORTING CIRCUIT; IMPLANTATION; MATHEMATICAL ANALYSIS; NEURAL PROSTHETIC SYSTEM; NONHUMAN; POWER SUPPLY; PRIORITY JOURNAL; PROCESS MONITORING; SEMICONDUCTOR; SIGNAL TRANSDUCTION;

ACTION POTENTIALS; ALGORITHMS; ANALOG-DIGITAL CONVERSION; BRAIN; ELECTRIC POWER SUPPLIES; ELECTROENCEPHALOGRAPHY; ENERGY TRANSFER; EQUIPMENT FAILURE ANALYSIS; FEASIBILITY STUDIES; HUMANS; NERVOUS SYSTEM DISEASES; PROSTHESES AND IMPLANTS; SIGNAL PROCESSING, COMPUTER-ASSISTED; THERAPY, COMPUTER-ASSISTED; USER-COMPUTER INTERFACE;

EID: 26444465132     PISSN: 15344320     EISSN: None     Source Type: Journal    
DOI: 10.1109/TNSRE.2005.854307     Document Type: Article

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