An equal area comparison of embedded DRAM and SRAM memory architectures for a chip multiprocessor

HP Laboratories Technical Report

Volumn , Issue 53, 2000, Pages

  Keltcher, Paul ^a   Richardson, Stephen ^a   Siu, Stuart ^a  

^a HEWLETT PACKARD LABORATORIES   (United States)

Author keywords

Cache hierarchy; Chip Multiprocessor; CMP; Embedded DRAM; Pageable memory

Indexed keywords

CACHES; CONSTANT SILICON AREA; MEMORY TADEOFFS;

DATA REDUCTION; DATA STORAGE EQUIPMENT; DYNAMIC RANDOM ACCESS STORAGE; ELECTRONIC COMMERCE; EMBEDDED SYSTEMS; MICROPROCESSOR CHIPS; SEMICONDUCTING SILICON;

COMPUTER ARCHITECTURE;

EID: 84862448424     PISSN: None     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article

References (24)

1. [Cri97] Richard Crisp. Direct Rambus Technology: The New Main Memory Standard. IEEE Micro, 17(6), November/December 1997.
2. [Dief99] Keith Diefendorff. Power4 Focuses on Memory Bandwidth. Microprocessor Report, 13(13), October 1999.
3. [Ham97] Lance Hammond, Basem A. Nayfeh and Kunle Olukotun. A Single-Chip Multiprocessor. IEEE Computer Special Issue on "Billion-Transistor Processors", September 1997.
4. [Ham98] Lance Hammond and Kunle Olukotun. Considerations in the Design of Hydra: A Multiprocessor-on-a-Chip Microarchitecture. Stanford University Technical Report CSL-TR-98-749, February 1998.
5. [Hun94] R. Hundal and V. G. Oklotdzija. Determination of Optimal Sizes for a First and Second level SRAM-DRAM On-Chip Cache Combination. Proceedings 1994 IEEE Conference on Computer Design: VLSI in Computers and Processors, October 1994.
6. [Ino97] Koji Inoue, Koji Kai and Kazuaki Murakami. Dynamically Variable Line-Size Cache Exploiting High On-Chip Memory Bandwidth of Merged DRAM/Logic LSIs. Japan-Germany Forum on Information Technology, November 1997.
7. th International Conference on High Performance Computing, Jan 1999.
8. th Annual International Symposium on Microarchitecture, December 1997.
9. [Kri99] Venkata Krishnan and Josep Torrellas. A Chip-Multiprocessor Architecture with Speculative Multithreading. IEEE Transactions on Computers, Special Issue on Multithreaded Architecture, September 1999.
10. [Mac99] Philip Machanick, Pierre Salverda and Lance Pompe. Hardware-Software Trade-offs in a Direct Rambus Implementation of the RAMpage Memory Hierarchy. 1999.
11. [MAT] Maflab, The MathWorks, Inc. Version 5.2.0.3084.
12. [Mul91] Johannes M. Mulder, Nhon T. Quach and Michael J. Flynn, "An Area Model for On-Chip Memories and its Application." TREE Journal of Solid-State Circuits, Vol. 26, No. 2, February 1991.
13. [Mur97] Kazuaki Murakami, Koji Inoue and Hiroshi Miyajima. Parallel Processing RAM (PPRAM). Kyushu University Technical Report PPRAM-TR-27, November 1997.
14. st International Symposium on Computer Architecture, February 1994.
15. [Olu96] Kunle Olukotun, Basem A. Nayfeh, Lance Hammond, Ken Wilson and Kun-Yung Chang. The Case for a Single-Chip Multiprocessor. In Proceedings of the Seventh International Symposium on Architectural Support for Parallel Languages and Operating Systems, October 1996.
16. [Olu99] Kunle Olukotun, Lance Hammond and Mark Willey. Improving the Performance of Speculative^ Parallel Applications on the Hydra CMP. In Proceedings of the 1999 ACM International Conference on Supercomputing, June 1999.
17. [Ram98] Rajesh Raman, Miron Livny and Marvin Solomon. Matchmaking: Distributed Resource Management for High Throughput Computing. In Proceedings of the Seventh IEEE International Symposium on High Performance Computing, July 1998.
18. [Sing92] J.P. Singh, W. Weber, A. Gupta. Splash: Stanford Parallel Applications for Shared Memory. Computer Architecture News, 20(1), 1992.
19. [SPEC] Standard Performance Evaluation Company (SPEC) Web Page, "http://www.spec.org".
20. [TPCC98] TPC-C Description, Transaction Processing Performance Council Web Page, "http://www.tpc.org/faq_TPCC.html".
21. th Annual International Symposium on Computer Architecture, June 1997.
22. [Wils99] Kenneth Wilson. The Use of DRAM in Processor Cache Design. To be published. February 2000.
23. nd Annual International Symposium on Computer Architecture, June 1995.
24. [Yam97] Tadaaki Yamauchi, Lance Hammond and Kunle Olukotun. A Single Chip Multiprocessor Integrated with DRAM. Stanford University Technical Report CSL-TR-97-731, August 1997.