Transparent dynamic optimization

HP Laboratories Technical Report

Volumn , Issue 77, 1999, Pages

  Bala, Vasanth ^a   Duesterwald, Evelyn ^a   Banerjia, Sanjeev ^a  

^a HEWLETT PACKARD LABORATORIES   (United States)

Author keywords

Code cache; Compilers; Dynamic optimization; Performance; Runtime optimization

Indexed keywords

CODE CACHE; DYNAMIC OPTIMIZATION; RUNTIME OPTIMIZATION;

C (PROGRAMMING LANGUAGE); CACHE MEMORY; CODES (SYMBOLS); COMPUTER ARCHITECTURE; COMPUTER OPERATING SYSTEMS;

PROGRAM COMPILERS;

EID: 84862447194     PISSN: None     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article

References (33)

1. Auslander, J., Philipose, M., Chambers, C., Eggers, S.J., and Bershad, B.N. 1996. Fast, effective dynamic compilation. In Proceedings of the SIGPLAN'96 Conference on Programming Language Design and Implementation (PLDI'96).
2. Bala, V., Duesterwald, E., and Banerjia, S. 1999. Transparent Dynamic Optimization: The Design and Implementation of Dynamo. Hewlett Packard Laboratories technical report, June 1999.
3. Bala, V. and Freudenberger, S. 1996. Dynamic optimization: the DYNAMO project at HP Labs Cambridge (project proposal). Hewlett Packard Laboratories internal memo, Feb 1996.
4. th Annual International Symposium on Microarchitecture (MICRO-29), Paris. 46-57.
5. Bedichek, R. 1995. Talisman: fast and accurate multicomputer simulation. In Proceeding 1995 ACM SIGMETRICS Conference on Measurement and Modeling of Computer Systems.
6. Chernoff, A., Herdeg, M., Hookway, R., Reeve, C., Rubin, N., Tye, T., Yadavalli, B., and Yates, J. 1998. FX!32: a profile-directed binary translator. IEEE Micro, Vol 18, No. 2, March/April 1998.
7. Cmelik, R.F. and Keppel, D. 1993. Shade: a fast instruction set simulator for execution profiling. Technical Report UWCSE-93-06-06, Dept. Comp. Science and Engineering, Univ. Washington.
8. Consel, C. and Noel, F. 1996. A general approach for run-time specialization and its application to C. In Proceedings of the 23th Annual Symposium on Principles of Programming Languages. 145-156.
9. th Annual International Symposium on Microarchitecture (MCRO-28). 208-218.
10. Cramer, T., Friedman, R., Miller, T., Seberger, D., Wilson, R., and Wolczko, M. 1997. Compiling Java Just In Time. IEEE Micro, May/Jun 1997.
11. th Annual International Symposium on Computer Architecture. 26-37.
12. Ebcioglu K., Altman, E.R., Sathaye, S, and Geschwind, M. 1999. Execution-based scheduling for VLIW architectures. To appear in Euro-Par, August '99, Toulouse, France.
13. Engler, D.R. 1996. VCODE: a retargetable, extensible, very fast dynamic code generation system. In Proceedings of the SIGPLAN'96 Conference on Programming Language Design and Implementation (PLDI'96).
14. st Annual Internation Symposium on Microarchitecture (MCRO-31), Dallas. 173-181.
15. Griswold, D. 1998. The Java HotSpot virtual machine architecture. Sun Microsystems, Mar. 1998. Available from http://java.sun.com/products/hotspot/ whitepaper.html.
16. Herold, S.A. 1998. Using complete machine simulation to understand computer system behavior. PhD. thesis, Dept. Computer Science, Stanford University.
17. Hohensee, P., Myszewski, M., and Reese, D. 1996. Wabi CPU emulation. In Proceedings Hot Chips VIII.
18. Holzle, U. 1994. Adaptive optimization for SELF: reconciling high performance with exploratory programming. PhD thesis, Computer Science Dept., Stanford University, available as Technical Report STAN-CS-TR-94-1520. Also available as a Sun Microsystems Lab technical report.
19. Insignia 1991. SoftWindows for Macintosh and UNIX. http://www.insignia. com.
20. th Ann. Microprocessor Forum, San Jose, CA.
21. Kelly, E.K., Cmelik, R.F., and Wing, M.J. 1998. Memory controller for a microprocessor for detecting a failure of speculation on the physical nature of a component being addressed. U.S. Patent 5,832,205, Nov. 1998.
22. Kumar, A. 1996. The HP PA-8000 RISC CPU: a high performance out-of-order processor. In Proceedings Hot Chips VIII, Palo Alto, CA.
23. Leone, M. and Dybvig, R.K. 1997. Dynamo: a staged compiler architecture for dynamic program optimization. Technical Report #490, Dept. Computer Science, Indiana University.
24. Leone, M. and Lee, P. 1996. Optimizing ML with run-time code generation. In Proceedings of the SIGPLAN'96 Conference on Programming Language Design and Implementation. 137-148.
25. May, C. 1987. Mimic: a fast System/370 simulator. ACM SIGPLAN 1987 Symposium on Interpreters and Interpretive techniques.
26. Papworth, D. 1996. Tuning the Pentium Pro microarchitecture. IEEE Micro, (Apr.). 8-15.
27. Peleg, A. and Weiser, U. 1994. Dynamic flow instruction cache memory organized around trace segments independent of virtual address line. U.S. patent 5,381,533.
28. Poletta, M., Engler, D.R., and Kaashoek, M.F. 1997. tcc: a system for fast flexible, and high-level dynamic code generation. In Proceedings of the SIGPLAN '97 Conference on Programming Language Design and Implementation. 109-121.
29. th Annual International Symposium on Microarchitecture (MICRO-29), Paris. 24-35.
30. Sannella, M., Maloney, J., Freeman-Benson, B., and Borning, A. 1993. Multi-way versus one-way constraints in user interfaces: experiences with the DeltaBlue algorithm. Software - Practice and Experience 23, 5 (May). 529-566.
31. Sites, R.L., Chernoff, A., Kirk, M.B., Marks, M.P., and Robinson, S.G. Binary Translation. Digital Technical Journal, Vol 4, No. 4, Special Issue, 1992.
32. Stears, P. 1994. Emulating the x86 and DOS/Windows in RISC environments. In Proceedings Microprocessor Forum, San Jose, CA.
33. Witchel, E. and Rosenblum R. 1996. Embra: fast and flexible machine simulation. In Proceedings of the SIGMETRICS '96 Conference on Measurement and Modeling of Computer Systems. 68-78.