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Volumn , Issue , 2012, Pages 93-98

Stability and yield-oriented ultra-low-power embedded 6T SRAM cell design optimization

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS;

EID: 84862074877     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/date.2012.6176439     Document Type: Conference Paper
Times cited : (10)

References (9)
  • 2
    • 33746369469 scopus 로고    scopus 로고
    • Static noise margin variation for sub-threshold SRAM in 65-nm CMOS
    • Calhoun, B.H. et al., "Static noise margin variation for sub-threshold SRAM in 65-nm CMOS", IEEE Journal of Solid-State Circuits, Volume: 41, 2006
    • (2006) IEEE Journal of Solid-State Circuits , vol.41
    • Calhoun, B.H.1
  • 3
    • 44849133673 scopus 로고    scopus 로고
    • Statistical modeling for the minimum standby supply voltage of a full SRAM array
    • J. Wang et al., "Statistical modeling for the minimum standby supply voltage of a full SRAM array," in Proc. Eur. Solid State Circuits Conf., 2007, pp. 400-403.
    • Proc. Eur. Solid State Circuits Conf., 2007 , pp. 400-403
    • Wang, J.1
  • 6
    • 0023437909 scopus 로고
    • Static-Noise Margin Analysis of MOS SRAM Cells
    • OCTOBER
    • E. Seevinck et al., "Static-Noise Margin Analysis of MOS SRAM Cells" IEEE Journal of Solid-State Circuits, VOL. SC-22, NO. 5, OCTOBER 1987
    • (1987) IEEE Journal of Solid-State Circuits , vol.SC-22 , Issue.5
    • Seevinck, E.1
  • 7
    • 78649923019 scopus 로고    scopus 로고
    • UT2B-FDSOI Device Architecture Dedicated to Low Power Design Techniques
    • J-P. Noel, et al., "UT2B-FDSOI Device Architecture Dedicated to Low Power Design Techniques," ESSDERC 2010
    • (2010) ESSDERC
    • Noel, J.-P.1
  • 8
    • 79960844325 scopus 로고    scopus 로고
    • On the variability in Planar FDSOI technology: From MOSFETs to SRAM cells
    • J. Mazurier, et al., "On the variability in Planar FDSOI technology: from MOSFETs to SRAM cells", IEEE Transactions on Electron Devices 2011
    • (2011) IEEE Transactions on Electron Devices
    • Mazurier, J.1
  • 9
    • 78349275034 scopus 로고    scopus 로고
    • An SNM Estimation and Optimization Model forULP sub-45nm CMOS SRAM in the Presence of Variability
    • A. Makosiej, et al., "An SNM Estimation and Optimization Model forULP sub-45nm CMOS SRAM in the Presence of Variability,"NEWCAS 2010
    • (2010) NEWCAS
    • Makosiej, A.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.