Integrated hardware architecture for efficient computation of the n-Best Bio-sequence local alignments in embedded platforms

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 20, Issue 7, 2012, Pages 1262-1275

  Sebastião, Nuno ^a   Roma, Nuno ^a   Flores, Paulo ^a  

^a INESC ID   (Portugal)

Author keywords

DNA sequence alignment; hardware accelerator; Smith Waterman (S W); Waterman Eggert (W E)

Indexed keywords

ACCELERATOR ARCHITECTURES; ALIGNMENT SYSTEM; COMPUTATIONAL REQUIREMENTS; CONSTRAINED SYSTEMS; DNA SEQUENCE ALIGNMENTS; EFFICIENT COMPUTATION; EMBEDDED PLATFORMS; GENERAL PURPOSE PROCESSORS; HARDWARE ACCELERATORS; HARDWARE ARCHITECTURE; HIGHER FREQUENCIES; LOCAL ALIGNMENT; SEQUENCE ALIGNMENTS; SEQUENCE PAIR; SMITH-WATERMAN; TRACEBACK; WATERMAN-EGGERT (W-E);

ALGORITHMS; ALIGNMENT; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); HARDWARE; PROGRAM PROCESSORS;

COMPUTATIONAL EFFICIENCY;

EID: 84862024420     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2011.2157541     Document Type: Article

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