GDDR5 Training - Challenges and solutions for ATE-based test

Proceedings of the Asian Test Symposium

Volumn , Issue , 2008, Pages 423-428

  Werkmann, Hubert ^a   Dong Myong, Kim ^a   Fujita, Shinji ^b  

^a Verigy Germany GmbH   (Germany)

^b Verigy ^*

Author keywords

[No Author keywords available]

Indexed keywords

DATA PATHS; DATA RATES; HIGH SPEEDS; SYSTEM COSTS; TIMING MARGINS; TWO LINKS; WORK IN PROGRESSES;

DATA STORAGE EQUIPMENT; POLYCHLORINATED BIPHENYLS; SPECIFICATIONS; STANDARDS; TIME MEASUREMENT;

TESTING;

EID: 58249120001     PISSN: 10817735     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ATS.2008.67     Document Type: Conference Paper

References (3)

1. JEDEC Committee JC42.3B ballot items 1733.01, 1733.12, 1733.13, 1733.14, 1733.36
2. "Qimonda GDDR5 - Whitepaper," August 2007
3. Gerd Haensel, K. Stieglbauer, G. Schulze, J. Moreira, "Implementation of an Economic Jitter Compliance Test for a Multi-Gigabit Device on ATE," IEEE International Test Conference 2004