A 2.5-GHz, 6.9-mW, 45-nm-LP CMOS, ΔΣ modulator based on standard cell design with time-interleaving

IEEE Journal of Solid-State Circuits

Volumn 45, Issue 7, 2010, Pages 1410-1420

  Madoglio, Paolo ^a   Ravi, Ashoke ^a   Cuellar, Luis ^a   Pellerano, Stefano ^a   Seddighrad, Parmoon ^b   Lomeli, Ismael ^a   Palaskas, Yorgos ^a  

^a INTEL CORPORATION   (United States)

^b University of Washington   (United States)

Author keywords

Digital Delta Sigma modulator (DSM); multi stage noise shaping (MASH); pipelining; time interleaving

Indexed keywords

BIT STREAM; CRITICAL PATHS; DELAY STAGES; DELTA SIGMA MODULATOR; DESIGN TIME; DIGITAL DESIGN TOOLS; DIGITAL DESIGNS; HIGH RATE; HIGH-SPEED; MULTI-STAGE; NOISE-SHAPING; PIPELINE SECTIONS; SAMPLING RATES; SECOND ORDERS; STANDARD CELL; STANDARD CELL DESIGN; TIME-INTERLEAVED; TIME-INTERLEAVING; TIME-TO-MARKET;

DELTA SIGMA MODULATION; DESIGN; ELECTRIC BATTERIES; STANDARDS;

MODULATORS;

EID: 77954148158     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2010.2048086     Document Type: Conference Paper

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