13% Power reduction in 16b integer unit in 40nm CMOS by adaptive power supply voltage control with Parity-based Error Prediction and Detection (PEPD) and fully integrated digital LDO

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 55, Issue , 2012, Pages 486-487

  Hirairi, Koji ^a   Okuma, Yasuyuki ^a   Fuketa, Hiroshi ^b   Yasufuku, Tadashi ^b   Takamiya, Makoto ^b   Nomura, Masahiro ^a   Shinohara, Hirofumi ^a   Sakurai, Takayasu ^b  

^a SEMICONDUCTOR TECHNOLOGY ACADEMIC RESEARCH CENTER   (Japan)

^b UNIVERSITY OF TOKYO   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CIRCUIT DELAYS; EFFICIENCY BENEFITS; ERROR PREDICTION; FULLY INTEGRATED; POWER REDUCTIONS; POWER SUPPLY VOLTAGE; PVT VARIATIONS; SCALING POWER; TIMING MARGIN; ULTRALOW VOLTAGE;

ENERGY EFFICIENCY; LOGIC CIRCUITS;

TIMING CIRCUITS;

EID: 84860653751     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2012.6177102     Document Type: Conference Paper

References (4)

1. S. Sridhara, et al., "Microwatt Embedded Processor Platform for Medical System-on-Chip Applications," IEEE Symp. VLSI Circuits, pp. 15-16, 2010.
2. Y. Okuma, et al., "0.5-V Input Digital LDO with 98.7% Current Efficiency and 2.7-mA Quiescent Current in 65nm CMOS," IEEE Custom Integrated Circuits Conf., pp. 323-326, 2010.
3. T. Nakura, et al., "Fine-Grain Redundant Logic Using Defect-Prediction Flip-Flops," ISSCC Dig. Tech. Papers, pp. 402-403, 2007.
4. DD) Scaling from 1.2V to 310mV Enabled by Contention-less Flip-Flops (CLFF) and Separated VDD between Flip-Flops and Combinational Logics," IEEE International Symp. Low Power Electronics and Design, pp. 163-168, 2011.