12.7-times energy efficiency increase of 16-bit integer unit by power supply voltage (VDD) scaling from 1.2V to 310mV enabled by contention-less flip-flops (CLFF) and separated VDD between flip-flops and combinational logics

Proceedings of the International Symposium on Low Power Electronics and Design

Volumn , Issue , 2011, Pages 163-168

  Fuketa, Hiroshi ^a   Hirairi, Koji ^b   Yasufuku, Tadashi ^a   Takamiya, Makoto ^a   Nomura, Masahiro ^b   Shinohara, Hirofumi ^b   Sakurai, Takayasu ^a  

^a INSTITUTE OF INDUSTRIAL SCIENCE   (Japan)

^b SEMICONDUCTOR TECHNOLOGY ACADEMIC RESEARCH CENTER   (Japan)

Author keywords

flip flop; subthreshold circuit; variations

Indexed keywords

CMOS PROCESSS; COMBINATIONAL LOGIC; EFFICIENCY INCREASE; FABRICATED CHIPS; FLIP-FLOP; MEASUREMENT RESULTS; MEDIA PROCESSING; OPERATING VOLTAGE; POWER SUPPLY VOLTAGE; SUBTHRESHOLD CIRCUITS; VARIATIONS;

CMOS INTEGRATED CIRCUITS; FLIP FLOP CIRCUITS; LOW POWER ELECTRONICS; POWER ELECTRONICS;

ENERGY EFFICIENCY;

EID: 80052722887     PISSN: 15334678     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISLPED.2011.5993630     Document Type: Conference Paper

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