0.5-V input digital LDO with 98.7% current efficiency and 2.7-μA quiescent current in 65nm CMOS

Proceedings of the Custom Integrated Circuits Conference

Volumn , Issue , 2010, Pages

  Okuma, Yasuyuki ^a   Ishida, Koichi ^b   Ryu, Yoshikatsu ^a   Zhang, Xin ^b   Chen, Po Hung ^b   Watanabe, Kazunori ^a   Takamiya, Makoto ^b   Sakurai, Takayasu ^b  

^a SEMICONDUCTOR TECHNOLOGY ACADEMIC RESEARCH CENTER   (Japan)

^b UNIVERSITY OF TOKYO   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CURRENT EFFICIENCY; INPUT VOLTAGES; LOAD CURRENTS; LOW NOISE; OUTPUT VOLTAGES; POWER SUPPLY VOLTAGE; QUIESCENT CURRENTS;

DIGITAL INTEGRATED CIRCUITS; ENERGY EFFICIENCY; INTEGRATED CIRCUIT MANUFACTURE; INTEGRATED CIRCUITS; LOGIC CIRCUITS; OPERATIONAL AMPLIFIERS; SWITCHING CIRCUITS; THRESHOLD LOGIC;

ANALOG CIRCUITS;

EID: 78649818058     PISSN: 08865930     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/CICC.2010.5617586     Document Type: Conference Paper

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