DC offset error compensation for synchronous reference frame PLL in single-phase grid-connected converters

IEEE Transactions on Power Electronics

Volumn 27, Issue 8, 2012, Pages 3467-3471

  Hwang, Seon Hwan ^a   Liu, Liming ^b   Li, Hui ^b   Kim, Jang Mok ^c  

^a Kyungnam University   (South Korea)

^b FLORIDA STATE UNIVERSITY   (United States)

^c Pusan National University   (South Korea)

Author keywords

DC offset error; integral operation; phase locked loop (PLL); scaling error; single phase grid connected converter (SPGC); synchronous d axis voltage

Indexed keywords

COMPENSATION ALGORITHM; DC OFFSETS; DQ-FRAME; GRID FREQUENCY; GRID-CONNECTED CONVERTERS; INTEGRAL OPERATION; PLL SYSTEM; POWER CONVERSION SYSTEMS; PROPORTIONAL INTEGRAL CONTROLLERS; SYNCHRONOUS REFERENCE FRAME;

ALGORITHMS; ERRORS; PHASE LOCKED LOOPS;

DC POWER TRANSMISSION;

EID: 84860290287     PISSN: 08858993     EISSN: None     Source Type: Journal    
DOI: 10.1109/TPEL.2012.2190425     Document Type: Article

References (16)

1. Y. Xue, L. Chang, S. B. Kjaer, J. Bordonau, and T. Shimizu, "Topologies of single-phase inverters for small distributed power generators: An overview," IEEE Trans. Power Electron., vol. 19, no. 5, pp. 1305-1314, Sep. 2004.
2. S. B. Kjaer, J. K. Pedersen, and F. Blaabjerg, "A review of single-phase grid-connected inverters for photovoltaic modules," IEEE Trans. Ind. Appl., vol. 41, no. 5, pp. 1292-1306, Sep./Oct. 2005. (Pubitemid 41444647)
3. U. A. Miranda, M. Aredes, and L. G. B. Rolim, "Adq synchronous reference frame control for single-phase converters," in Proc. Power Electron. Spec. Conf., 2005, pp. 1377-1381. (Pubitemid 46379354)
4. M. Ciobotaru, V. G. Agelidis, R. Teodorescu, and F. Blaabjerg, "Accurate and less-disturbing active antiislanding method based on PLL for grid-connected converter," IEEE Trans. Power Electron., vol. 25, no. 6, pp. 1576-1584, Jun. 2010.
5. S.M. Silva, B. M. Lopes, B. J. C. Filho, R. P. Campana, and W. C. Bosventura, "Performance evaluation of PLL algorithms for single-phase gridconnected systems," in Proc. 39th IEEE Ind. Appl. Soc. Annu. Meet. Ind. Appl. Conf., 2004, vol. 4, pp. 2259-2263. (Pubitemid 40016393)
6. S. K. Chung, H. B. Shin, and H.W. Lee, "Precision control of single-phase PWMinverter using PLL compensation," in Proc. IEE Electr. Power Appl., Mar. 2005, vol. 152, no. 2, pp. 429-436. (Pubitemid 40564725)
7. P. Rodriguez, J. Pou, J. Bergas, J. I. Candela, R. P. Burgos, and D. Boroyevich, "Decoupled double synchronous reference frame PLL for power converters control," IEEE Trans. Power Electron., vol. 22, no. 2, pp. 584-592, Mar. 2007. (Pubitemid 46523183)
8. P. Xiao, K. A. Corzine, and G. K. Venayagamoorthy, "Multiple reference frame-based control of three-phase PWM boost rectifiers under unbalanced and distorted input conditions," IEEE Trans. Power Electron., vol. 23, no. 4, pp. 2006-2017, Jul. 2008.
9. M. Ciobotaru, R. Teodorescu, and F. Blaabjerg, "A new single-phase PLL structure based on second order generalized integrator," in Proc. Power Electron. Spec. Conf., 2006, pp. 1-6.
10. D. Velasco, C. Trujillo, G. Garcera, and E. Figueres, "An active antiislanding method based on phase-PLL perturbation," IEEE Trans. Power Electron., vol. 26, no. 4, pp. 1056-1066, Apr. 2011.
11. T. Thacker, D. Boroyevich, R. Burgos, and F.Wang, "Phase-locked loops noise reduction via phase detector implementation for single-phase systems," IEEE Trans. Ind. Electron., vol. 58, no. 6, pp. 2482-2490, Jun. 2011.
12. S. Shinnaka, "A novel fast-tracking D-estimation method for single-phase signals," IEEE Trans. Power Electron., vol. 26, no. 4, pp. 1081-1088, Apr. 2011.
13. S. J. Lee, J. K. Kim, and S. K. Sul, "A new phase detecting method for power conversion systems considering distorted conditions in power system," in Proc. 34th IEEE Ind. Appl. Soc. Annu. Meet. Ind. Appl. Conf., 1999, vol. 4, pp. 2167-2172.
14. S. K. Chung, "A phase tracking system for three phase utility interface inverters," IEEE Trans. Power Electron., vol. 15, no. 3, pp. 431-438, May 2000.
15. M. Ciobotaru, R. Teodorescu, and V. G. Agelidis, "Offset rejection for PLL based synchronization in grid-connected converters," in Proc. 23rd Annu. IEEE Appl. Power Energy Conf. Expo., 2008, pp. 1611-1617.
16. M. Karimi-Ghartemani, S. A. Khajehoddin, P. K. Jain, A. Bakhshai, and M. Mojiri, "Addressing DC component in PLL and notch filter algorithms," IEEE Trans. Power Electron., vol. 27, no. 1, pp. 78-86, Jan. 2012.