Evolutionary algorithms for global parametric fault diagnosis in analogue integrated circuits

Bulletin of the Polish Academy of Sciences: Technical Sciences

Volumn 60, Issue 1, 2012, Pages 133-142

  Jantos, P ^a   Grzechca, D ^a   Rutkowski, J ^a  

^a SILESIAN UNIVERSITY OF TECHNOLOGY   (Poland)

Author keywords

analogue integrated circuits; evolutionary algorithms; fault diagnosis; identification; localization

Indexed keywords

ANALOGUE INTEGRATED CIRCUITS; BAND PASS; CIRCUIT UNDER TEST; CLASSICAL METHODS; DIAGNOSIS METHODS; DIFFERENTIAL EVOLUTION; EVOLUTIONARY APPROACH; EVOLUTIONARY METHOD; GENE EXPRESSION PROGRAMMING; HEURISTIC APPROACH; LINEAR CLASSIFIERS; LOCALIZATION; NEAREST NEIGHBORHOOD; PARAMETRIC FAULT; PARAMETRIC FAULT DIAGNOSIS; PRODUCTION PHASE;

BANDPASS FILTERS; EVOLUTIONARY ALGORITHMS; FAILURE ANALYSIS; HEURISTIC METHODS; IDENTIFICATION (CONTROL SYSTEMS); OPERATIONAL AMPLIFIERS; OSCILLATORS (ELECTRONIC);

LINEAR INTEGRATED CIRCUITS;

EID: 84860151930     PISSN: 02397528     EISSN: None     Source Type: Journal    
DOI: 10.2478/v10175-012-0019-4     Document Type: Article

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