Design of self-checking fully differential circuits and boards

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 8, Issue 2, 2000, Pages 113-128

  Lubaszewski, Marcelo ^b   Mir, Salvador ^a,c   Kolarik, Vladimir ^d   Nielsen, Christian ^e   Courtois, Bernard ^a,c  

^a IEEE   (Serbia)

^b Federal University of Rio Grande do Sul   (Serbia)

^c TIMA LABORATORY   (France)

^d BRNO UNIVERSITY OF TECHNOLOGY   (Czech Republic)

^e DEIF A S   (Denmark)

Author keywords

[No Author keywords available]

Indexed keywords

INTEGRATED CIRCUIT LAYOUT; INTEGRATED CIRCUIT TESTING; MIXER CIRCUITS; PRINTED CIRCUIT BOARDS; THRESHOLD VOLTAGE;

LINEAR FULLY DIFFERENTIAL (FD) CIRCUITS; TOTALLY SELF-CHECKING (CM);

LINEAR INTEGRATED CIRCUITS;

EID: 0033871258     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/92.831432     Document Type: Article

References (21)

1. P. R. Gray, B. A. Wooley, and R. W. Brodersen, Eds., Analog MOS Integrated Circuits, II. New York: IEEE Press, 1989.
2. M. Lubaszewski and B. Courtois, "On the design of self-checking boundary scannable boards," in Int. Test Conf., 1992, pp. 372-381.
3. IEEE Standard Test Access Port and Boundary Scan Architecture, IEEE Standard 1149.1-1990, 1990.
4. M. Nicolaidis, "A unified built-in self-test scheme: UBIST," in 18th Int. Symp. Fault Tolerant Computing, Tokyo, Japan, 1988, pp. 157-163.
5. A. Chatterjee, "Concurrent error detection in linear analog and switched-capacitor state variable systems using continuous checksums," in IEEE Int. Test Conf., 1991, pp. 582-591.
6. J. L. Huertas, D. Vázquez, and A. Rueda, "On-line testing of switched-capacitor filters," in IEEE VLSI Test Symp., 1992, pp. 102-106.
7. S. Krishnan, S. Sahli, and C. Wey, "Test generation and concurrent error detection in current-mode A/D converters," in Proc. Int. Test Conf., 1992, pp. 312-320.
8. V. Kolarik, M. Lubaszewski, and B. Courtois, "Toward self-checking mixed-signal integrated circuits," in European Solid-State Circuits Conf., Seville, Spain, Sept. 1993, pp. 202-205.
9. B. Vinnakota and R. Harjani, "The design of analog self-checking circuits," in 7th Int. Conf. VLSI Design, Jan. 1994, pp. 67-70.
10. W. C. Carter and P. R. Schneider, "Design of dynamically checked computers," in Proc. IFIP Congress, Edinburgh, U.K., 1968.
11. D. A. Anderson, "Design of self-checking digital networks using coding techniques," Univ. Illinois, Urbana, Sept. 1971.
12. J. E. Smith and G. Metze, "Strongly fault secure logic networks," IEEE Trans. Comput., vol. C-27, June 1978.
13. M. Nicolaidis, I. Jansch, and B. Courtois, "Strongly code disjoint checkers," in 14th Int. Symp. Fault Tolerant Computing, Kissemmee, FL, June 1984.
14. M. Nicolaidis, "Self-exercising checkers for unified built-in self-test (UBIST)," IEEE Trans. Computer-Aided Design, vol. 8, pp. 203-218, Mar. 1989.
15. V. Kolarik, S. Mir, M. Lubaszewski, and B. Courtois, "Analogue checkers with absolute and relative tolerances," IEEE Trans. Computer-Aided Design, vol. 14, pp. 607-612, May 1995.
16. M. Nicolaidis, "Finitely self-checking circuits and their application on current sensors," in IEEE VLSI Test Symp., 1993, pp. 66-69.
17. S. Mir, V. Kolarik, M. Lubaszewski, and D. Vázquez, "Detectability of differential bridges in balanced circuits," in IEEE Int. Mixed Signal Testing Workshop, Quebec City, Canada, May 1996, pp. 23-28.
18. P. W. Li, M. J. Chin, P. R. Gray, and R. Castello, "A ratio-independent algorithmic analog-to-digital conversion technique," IEEE J. Solid-State Circuits, vol. SC-19, pp. 828-836, Dec. 1984.
19. M. Nicolaidis, private communication, June 1995.
20. S. Mir, V. Kolarik, M. Lubaszewski, C. Nielsen, and B. Courtois, "Built-in self-test and fault diagnosis of fully differential analogue circuits," in 12th IEEE Int. Conf. Computer-Aided Design, San Jose, CA, Nov. 1994, pp. 486-490.
21. V. Kolarik, M. Lubaszewski, and B. Courtois, "Designing self-exercising analogue checkers," in 12th IEEE VLSI Test Symp., Cherry Hill, NJ, Apr. 1994, pp. 252-257.