Solid state bonding of silicon chips to silver buffer on copper substrates

IEEE Transactions on Components, Packaging and Manufacturing Technology

Volumn 2, Issue 2, 2012, Pages 194-198

  Sha, Chu Hsuan ^a   Lee, Chin C ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

Annealing; copper substrate; electroplating; microstructure; silicon chips; silver; solid state bonding

Indexed keywords

AG ATOMS; ALL METAL; ATOMIC SCALE; BONDED STRUCTURE; BONDING INTERFACES; BONDING MEDIUM; BONDING PROCESS; CLOSE PROXIMITY; COPPER SUBSTRATE; COPPER SUBSTRATES; CROSS SECTION; CU SUBSTRATE; DUCTILE PROPERTIES; ELECTRONIC PACKAGING; GRAIN SIZE; HIGH MELTING; HIGH OPERATING TEMPERATURE; LOW-YIELD-STRENGTHS; MOLTEN PHASE; SCANNING ELECTRON MICROSCOPE; SI CHIPS; SILICON CHIP; SILICON CHIPS; SOLID STATE BONDING; STATIC PRESSURE;

ANNEALING; ATOMS; CHROMIUM; COPPER; ELECTRONICS PACKAGING; ELECTROPLATING; GOLD; GOLD COATINGS; MELTING POINT; MICROSTRUCTURE; SCANNING ELECTRON MICROSCOPY; SILICON; SUBSTRATES; THERMAL CONDUCTIVITY;

SILVER;

EID: 84859034200     PISSN: 21563950     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCPMT.2011.2161085     Document Type: Article

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