Classifying Interprocess Communication in Process Network Representation of Nested-Loop Programs

ACM Transactions on Embedded Computing Systems

Volumn 6, Issue 2, 2007, Pages 13-

  Turjan, Alexandru ^a   Kienhuis, Bart ^a   Deprettere, E D ^a  

^a RWTH AACHEN UNIVERSITY   (Germany)

Author keywords

Classification of Interprocess Communication; hybrid classification approach; integer linear programming; matrix manipulations; Nested Loop Programs; Process Networks; Static analysis

Indexed keywords

EID: 84857211140     PISSN: 15399087     EISSN: 15583465     Source Type: Journal    
DOI: 10.1145/1234675.1234680     Document Type: Article

References (50)

1. Basten, T. And Hoogerbrugge, J. 2001. Efficient execution of process networks. In Communicating Process Architectures - 2001, Proceedings. Bristol. 1-14.
2. Clauss, P. 1996. Counting solutions to linear and nonlinear constraints through ehrhart polynomials: Applications to analyse and transform scientific programs. In 10th International Conference on Supercomputing, Philadelphia, PA.
3. Davis, Jr, Ii, J., Hylands, C., Kienhuis, B., Lee, E. A., Liu, J., Liu, X., Muliadi, L., Neuendorffer, S., Tsay, J., Vogel, B., And Xiong, Y. 2001. Heterogeneous Concurrent modeling and design in java. Tech. Rep. Memorandum UCB/ERL M01/12 (Mar.), University of California, Dept EECS, Berkeley, CA 94720.
4. De Greef, E., Catthoor, F., And De Man, H. 1977. Memory size reduction through storage order optimization for embedded parallel multimedia applications. In Parallel Processing and Multimedia. Geneva.
5. De Kock, E., Essink, G., Smits, W., Van Der Wolf, P., Brunel, J.-Y., Kruijtzer, W., Lieverse, P., And Vissers, K. 2000. YAPI: Application modeling for signal processing systems. In Proc. 37th Design Automation Conference (DAC'2000). Los Angeles, CA. 402-405.
6. FeautrieR, P. 1988. Parametric Integer Programming. In RAIRO Recherche Op?rationnelle, 22, 3, 243-268.
7. Kahn, G. 1974. The semantics of a simple language for parallel programming. In Proc. of the IFIP Congress 74. North-Holland, Amsterdam.
8. Kienhuis, B., Rypkema, E., And Deprettere, E. 2000. Compaan: Deriving process networks from matlab for embedded signal processing architectures. In Proceedings of the 8th International Workshop on Hardware/Software Codesign (CODES). San Diego, CA.
9. Kienhuis, B., Deprettere, E., Van Der Wolf, P., And Vissers, K. 2002. A Methodology to Design Programmable Embedded Systems. Lncs, vol. 2268. Springer Verlag, New York, 18-37.
10. Lefebvre, V. And Feautrier, P. 1998. Automatic storage management in paralel programs. Vol. 24. Parallel Computing. 649-671.
11. Nemhauser, G. And Wolsey, L. 1988. Integer and Combinatorial Optimization. Wiley-Interscience, New York.
12. Parks, T. 1995. Bounded scheduling of process networks. Ph.D. thesis, EECS Department, University of California, Berkeley. Picochip. 2000. http://www.picochip.com.
13. Pugh, W. 1992. The Omega test: A fast and practical integer programming algorithm for dependence analysis. Communications of the ACM 35, 8, 102-114.
14. Quillere, F. And Rajopadhye, S. 2000. Optimizing memory usage in the polyhedral model. In ACM Transactions on Programming Languages and Systems. Vol. 22. 773-815.
15. Rijpkema, E. 2002. Modeling task level parallelism in piece-wise regular programs. PhD thesis, Leiden Institute of Advanced Computer Science, Leiden Univerity, The Netherlands.
16. Schrijver, A. 1986. Theory of Linear and Integer Programming. Wiley, New York.
17. Stefanov, T. And Deprettere, E. 2003. Deriving process networks from weakly dynamic applicatIons In System-Level Design. In Proc. Ieee-Acm-Ifip International Conference On Hardware/Software Codesign And System Synthesis (Codes + Isss'03). Newport Beach, Ca. 90-96.
18. Stefanov, T., Zissulescu, C., Turjan, A., Kienhuis, B., And Deprettere, E. 2004. System Design Using Kahn Process Networks: The Compaan/Laura Approach. In Proceedings Of Date2004. Paris.
19. Stravers, P. And Hoogerbrugge, J. 2001. Homogeneous multiprocessoring and the future of silicon Design Paradigms. In Proceedings Of The Int. Symposium On Vlsi Technology, Systems, And Applications.
20. Teich, J. And Thiele, L. 1993. Partitioning of processor arrays: A piecewise regular approach. Integration, the VLSI Journal 14, 297-332.
21. Turjan, A. And Kienhuis, B. 2003. Storage management in process networks using the lexicographically maximal preimage. In Proceedings of the IEEE 14thInt. Conf. on Application-specific Systems, Architectures and Processors (ASAP'03). The Hague.
22. Turjan, A., Kienhuis, B., And Deprettere, E. 2002. A compile time based approach for solving out-of-order communication in kahn process networks. In Proceedings of the IEEE 13th International Conference on Application-specific Systems, Architectures and Processors (Asap'02). San Jose, CA.
23. Turjan, A., Kienhuis, B., And Deprettere, E. 2004. Translating affine nested loops to Process Networks. In International Conference on Compilers, Architectures and Synthesis for Embedded Systems (CASES). Washington D.C.
24. Wilde, D. And Rajopadhye, S. 2002. Memory reuse in the polyhedral model. In In Proc. Euro-Par'96.
25. Clauss, P. 1996. Counting solutions to linear and nonlinear constraints through ehrhart polynomials: Applications to analyse and transform scientific programs. In 10th International Conference on Supercomputing, Philadelphia, PA.
26. Davis, Jr, Ii, J., Hylands, C., Kienhuis, B., Lee, E. A., Liu, J., Liu, X., Muliadi, L., Neuendorffer, S., Tsay, J., Vogel, B., And Xiong, Y. 2001. Heterogeneous concurrent modeling and design in java. Tech. Rep. Memorandum UCB/ERL M01/12 (Mar.), University of California, Dept EECS, Berkeley, CA 94720.
27. De Greef, E., Catthoor, F., And De Man, H. 1977. Memory size reduction through storage order optimization for embedded parallel multimedia applications. In Parallel Processing and Multimedia. Geneva.
28. De Kock, E., Essink, G., Smits, W., Van Der Wolf, P., Brunel, J.-Y., Kruijtzer, W., Lieverse, P., And Vissers, K. 2000. Yapi: Application modeling for signal processing systems. In Proc. 37th Design Automation Conference (DAC'2000). Los Angeles, CA. 402-405.
29. Feautrier, P. 1988. Parametric Integer Programming. In RAIRO Recherche Op?rationnelle, 22, 3, 243-268.
30. Kahn, G. 1974. The semantics of a simple language for parallel programming. In Proc. of the IFIP Congress 74. North-Holland, Amsterdam.
31. Kienhuis, B., Rypkema, E., And Deprettere, E. 2000. Compaan: Deriving process networks from matlab for embedded signal processing architectures. In Proceedings of the 8th International Workshop on Hardware/Software Codesign (CODES). San Diego, CA.
32. Kienhuis, B., Deprettere, E., Van Der Wolf, P., And Vissers, K. 2002. A Methodology to Design Programmable Embedded Systems. LNCS, vol. 2268. Springer Verlag, New York, 18-37.
33. Lefebvre, V. And Feautrier, P. 1998. Automatic storage management in paralel programs. Vol. 24. Parallel Computing. 649-671.
34. Nemhauser, G. And Wolsey, L. 1988. Integer and Combinatorial Optimization. Wiley-Interscience, New York.
35. Parks, T. 1995. Bounded scheduling of process networks. Ph.D. thesis, EECS Department, University of California, Berkeley.
36. Picochip. 2000. http://www.picochip.com.
37. Pugh, W. 1992. The Omega test: A fast and practical integer programming algorithm for dependence analysis. Communications of the ACM 35, 8, 102-114.
38. Quillere, F. And Rajopadhye, S. 2000. Optimizing memory usage in the polyhedral model. In ACM Transactions on Programming Languages and Systems. Vol. 22. 773-815.
39. Rijpkema, E. 2002. Modeling task level parallelism in piece-wise regular programs. PhD thesis, Leiden Institute of Advanced Computer Science, Leiden Univerity, The Netherlands.
40. Schrijver, A. 1986. Theory of Linear and Integer Programming. Wiley, New York.
41. Stefanov, T. And Deprettere, E. 2003. Deriving process networks from weakly dynamic applications in system-level design. In Proc. IEEE-ACM-IFIP International Conference on Hardware/Software Codesign and System Synthesis (Codes + Isss'03). Newport Beach, CA. 90-96.
42. Stefanov, T., Zissulescu, C., Turjan, A., Kienhuis, B., And Deprettere, E. 2004. System design using kahn process networks: The compaan/laura approach. In Proceedings of DATE2004. Paris.
43. Stravers, P. And Hoogerbrugge, J. 2001. Homogeneous multiprocessoring and the future of silicon design paradigms. In Proceedings of the Int. Symposium on VLSI Technology, Systems, and Applications.
44. TEich, J. And Thiele, L. 1993. Partitioning of processor arrays: A piecewise regular approach. Integration, the VLSI Journal 14, 297-332.
45. Turjan, A. And Kienhuis, B. 2003. Storage management in process networks using the lexicographically maximal preimage. In Proceedings of the IEEE 14thInt. Conf. on Application-specific Systems, Architectures and Processors (ASAP'03). The Hague.
46. Turjan, A., Kienhuis, B., And Deprettere, E. 2002. A compile time based approach for solving out-of-order communication in kahn process networks. In Proceedings of the IEEE 13th International Conference on Application-specific Systems, Architectures and Processors (ASAP'02). San Jose, CA.
47. Turjan, A., KienhuiS, B., And Deprettere, E. 2004. Translating affine nested loops to Process Networks. In International Conference on Compilers, Architectures and Synthesis for Embedded Systems (CASES). Washington D.C.
48. Wilde, D. And Rajopadhye, S. 2002. Memory reuse in the polyhedral model. In In Proc. Euro-Par 96. Lyon, France.
49. Xilinx. 2000. http://www.xilinx.com.
50. Zissulescu, C., Stefanov, T., Kienhuis, B., And Deprettere, E. 2003. LAURA: Leiden architecture research and exploration tool. In Proc. 13th Int. Conference on Field Programmable Logic and Applications (FPL'03).