Transistor matching and silicon thickness variation in ETSOI technology

Technical Digest - International Electron Devices Meeting, IEDM

Volumn , Issue , 2011, Pages

  Hook, Terence B ^a   Vinet, Maud ^b   Murphy, Richard ^a   Ponoth, Shom ^a   Grenouillet, Laurent ^b  

^a IBM MICROELECTRONICS   (United States)

^b LETI   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

EXPERIMENTAL MEASUREMENTS; SILICON ON INSULATOR; SILICON THICKNESS; SILICON WAFER PROCESSING; TRANSISTOR MATCHING;

ELECTRON DEVICES; THRESHOLD VOLTAGE;

SILICON ON INSULATOR TECHNOLOGY;

EID: 84856996002     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IEDM.2011.6131497     Document Type: Conference Paper

References (6)

1. O. Weber et al., "High Immunity to Threshold Voltage Variability in Undoped Ultra-Thin FDSOI MOSFETs and its Physical Understanding, "International Electron Devices Meeting 2008, pp. 1-4
2. Cheng et al., Extremely thin SOI (ETSOI) CMOS with record low variability for low power system-on-chip applications," International Electron Devices Meeting 2009, pp. 1-4
3. Q. Liu et al. "Ultra-Thin-Body and Box (UTBB) Fully Depleted (FD) Device Integration for 22nm Node and Beyond." International Symposium on VLSI 2010, pp. 61-62,
4. M. Pelgrom, A. Duinmaijer, and A. Welbers. "Matching Properties of MOS Transistors," J. Solid-State Circuits, 1989, pp. 1433-1440.
5. T. Hook et al. Trans. On Electron Dev., 2011, pp. 1255-56.
6. T. Poiroux et al., "New and accurate method for electrical extraction of silicon film thickness on fully-depleted SOI and double gate transistors, Proceedings of the IEEE International SOI Conference, 2004, pp. 73-74.