New and accurate method for electrical extraction of silicon film thickness on fully-depleted SOI and double gate transistors

Proceedings - IEEE International SOI Conference

Volumn , Issue , 2004, Pages 73-74

  Poiroux, T ^a   Widiez, J ^b   Lolivier, J ^a   Vinet, M ^a   Casse M ^a   Previtali B ^a   Deleonibus, S ^a  

^a CEA GRENOBLE   (France)

^b STMICROELECTRONICS   (France)

Author keywords

[No Author keywords available]

Indexed keywords

APPROXIMATION THEORY; CAPACITANCE; COMPUTER SIMULATION; ELECTRIC FIELDS; ELECTROSTATICS; EXTRACTION; GATES (TRANSISTOR); QUANTUM THEORY; SILICON ON INSULATOR TECHNOLOGY; THRESHOLD VOLTAGE;

DOUBLE GATE (DG) TRANSISTORS; GATE VOLTAGES; QUANTUM CONFINEMENT EFFECTS; SILICON-ON-INSULATOR FULLY-DEPLETED (FDSOI);

SEMICONDUCTING SILICON;

EID: 16244406804     PISSN: 1078621X     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)

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4. O.Faynot et al, Proc. of ESSDERC, p.807, 1992.
5. M.Cassé et al, Proc. of ESSDERC, p.87, 2003.