Bit-cell level optimization for non-volatile memories using magnetic tunnel junctions and spin-transfer torque switching

IEEE Transactions on Nanotechnology

Volumn 11, Issue 1, 2012, Pages 172-181

  Fong, Xuanyao ^a   Choday, Sri Harsha ^a   Roy, Kaushik ^a  

^a Purdue University   (United States)

Author keywords

Circuit optimization; magnetic memories; magnetic tunnel junctions (MTJ); memory architectures; spin transfer torque MRAM (STT MRAM) bit cells

Indexed keywords

CIRCUIT OPTIMIZATION; ELECTRICAL PARAMETER; GREENS FUNCTION METHOD; HIGH-DENSITY; HIGH-SPEED; LANDAU-LIFSHITZ-GILBERT EQUATIONS; LOW POWER; MAGNETIC MEMORIES; MAGNETIC RANDOM ACCESS MEMORIES; MAGNETIC TUNNEL JUNCTION; MAGNETIZATION DYNAMICS; MEMORY TECHNOLOGY; MIXED MODE SIMULATION; NON EQUILIBRIUM; NON-VOLATILE MEMORIES; ON CHIPS; OPTIMIZATION TECHNIQUES; SILICON-ON-INSULATOR CMOS; SIMULATION FRAMEWORK; SPIN TORQUE; SPIN TRANSFER TORQUE; SPIN-TRANSFER TORQUE MRAM (STT-MRAM) BIT-CELLS; TRANSISTOR SIZING; TRANSPORT PHYSICS; VERILOG-A;

CELLS; CMOS INTEGRATED CIRCUITS; MAGNETIC STORAGE; MAGNETISM; MEMORY ARCHITECTURE; MRAM DEVICES; OPTIMIZATION; RANDOM ACCESS STORAGE; SEMICONDUCTOR JUNCTIONS; SPIN DYNAMICS; TORQUE; TUNNEL JUNCTIONS;

MAGNETIC DEVICES;

EID: 84855642454     PISSN: 1536125X     EISSN: None     Source Type: Journal    
DOI: 10.1109/TNANO.2011.2169456     Document Type: Article

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