-
1
-
-
77951575084
-
Highthroughput Bayesian computing machine with reconfigurable hardware
-
Monterey, California, USA ACM
-
Lin M., Lebedev I., Wawrzynek J., Highthroughput Bayesian computing machine with reconfigurable hardware Proceedings of the 18th annual ACM/SIGDA International Symposium on Field Programmable Gate Arrays (FPGA '10) 2010 Monterey, California, USA ACM 73 82
-
(2010)
Proceedings of the 18th Annual ACM/SIGDA International Symposium on Field Programmable Gate Arrays (FPGA '10)
, pp. 73-82
-
-
Lin, M.1
Lebedev, I.2
Wawrzynek, J.3
-
3
-
-
79951735648
-
-
Wikipedia November
-
Wikipedia, C-to-hdl. November 2009, http://en.wikipedia.org/wiki/CtoHDL/
-
(2009)
C-to-hdl
-
-
-
5
-
-
0034174174
-
Garp architecture and C compiler
-
DOI 10.1109/2.839323
-
Callahan T. J., Hauser J. R., Wawrzynek J., Garp architecture and C compiler Computer 2000 33 4 62 69 (Pubitemid 30585677)
-
(2000)
Computer
, vol.33
, Issue.4
, pp. 62-69
-
-
Callahan, T.J.1
Hauser, J.R.2
Wawrzynek, J.3
-
6
-
-
12844273425
-
Spatial computation
-
October New York, NY, USA
-
Budiu M., Venkataramani G., Chelcea T., Goldstein S. C., Spatial computation Proceedings of the 11th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS-XI '04) October 2004 New York, NY, USA 14 26
-
(2004)
Proceedings of the 11th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS-XI '04)
, pp. 14-26
-
-
Budiu, M.1
Venkataramani, G.2
Chelcea, T.3
Goldstein, S.C.4
-
7
-
-
34548253874
-
RAMP: Research accelerator for multiple processors
-
DOI 10.1109/MM.2007.39
-
Wawrzynek J., Patterson D., Oskin M., Lu S. L., Kozyrakis C., Hoe J. C., Chiou D., Asanovi K., RAMP: research accelerator for multiple processors IEEE Micro 2007 27 2 46 57 (Pubitemid 47322500)
-
(2007)
IEEE Micro
, vol.27
, Issue.2
, pp. 46-57
-
-
Wawrzynek, J.1
Patterson, D.2
Oskin, M.3
Lu, S.-L.4
Kozyrakis, C.5
Hoe, J.C.6
Chiou, D.7
Asanovic, K.8
-
8
-
-
70350752429
-
Fcuda: Enabling efficient compilation of cuda kernels onto fpgas
-
San Francisco, Calif, USA
-
Papakonstantinou A., Gururaj K., Stratton J. A., Chen D., Cong J., Hwu M. W., Fcuda: enabling efficient compilation of cuda kernels onto fpgas Proceedings of the 7th IEEE Symposium on Application Specific Processors (SASP '09) 2009 San Francisco, Calif, USA
-
(2009)
Proceedings of the 7th IEEE Symposium on Application Specific Processors (SASP '09)
-
-
Papakonstantinou, A.1
Gururaj, K.2
Stratton, J.A.3
Chen, D.4
Cong, J.5
Hwu, M.W.6
-
9
-
-
79958706917
-
Synthesis of platform architectures from opencl programs
-
Salt Lake City, Utah, USA
-
Owaida M., Bellas N., Daloukas K., Antonopoulos C. D., Synthesis of platform architectures from opencl programs Proceedings of the 19th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM '11) 2011 Salt Lake City, Utah, USA
-
(2011)
Proceedings of the 19th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM '11)
-
-
Owaida, M.1
Bellas, N.2
Daloukas, K.3
Antonopoulos, C.D.4
-
10
-
-
45849134070
-
Sparse inverse covariance estimation with the graphical lasso
-
DOI 10.1093/biostatistics/kxm045
-
Friedman J., Hastie T., Tibshirani R., Sparse inverse covariance estimation with the graphical lasso Biostatistics 2008 9 3 432 441 (Pubitemid 351882084)
-
(2008)
Biostatistics
, vol.9
, Issue.3
, pp. 432-441
-
-
Friedman, J.1
Hastie, T.2
Tibshirani, R.3
-
11
-
-
34249761849
-
Learning Bayesian networks: The combination of knowledge and statistical data
-
Heckerman D., Geiger D., Chickering D. M., Learning Bayesian networks: the combination of knowledge and statistical data Machine Learning 1995 20 3 197 243
-
(1995)
Machine Learning
, vol.20
, Issue.3
, pp. 197-243
-
-
Heckerman, D.1
Geiger, D.2
Chickering, D.M.3
-
13
-
-
79952909372
-
Bridging the GPGPU-FPGA efficiency gap
-
New York, NY, USA
-
Fletcher C., Lebedev I., Asadi N., Burke D., Wawrzynek J., Bridging the GPGPU-FPGA efficiency gap Proceedings of the 19th ACM/SIGDA International Symposium on Field Programmable Gate Arrays (FPGA '11) 2011 New York, NY, USA 119 122
-
(2011)
Proceedings of the 19th ACM/SIGDA International Symposium on Field Programmable Gate Arrays (FPGA '11)
, pp. 119-122
-
-
Fletcher, C.1
Lebedev, I.2
Asadi, N.3
Burke, D.4
Wawrzynek, J.5
-
14
-
-
77954756015
-
Paralearn: A massively parallel, scalable system for learning interaction networks on fpgas
-
Ibaraki, Japan ACM
-
Bani Asadi N., Fletcher C. W., Gibeling G., Paralearn: a massively parallel, scalable system for learning interaction networks on fpgas Proceedings of the 24th ACM International Conference on Supercomputing 2010 Ibaraki, Japan ACM 83 94
-
(2010)
Proceedings of the 24th ACM International Conference on Supercomputing
, pp. 83-94
-
-
Bani Asadi, N.1
Fletcher, C.W.2
Gibeling, G.3
-
16
-
-
49549100459
-
Learning causal Bayesian network structures from experimental data
-
Ellis B., Wong W. H., Learning causal Bayesian network structures from experimental data Journal of the American Statistical Association 2008 103 482 778 789
-
(2008)
Journal of the American Statistical Association
, vol.103
, Issue.482
, pp. 778-789
-
-
Ellis, B.1
Wong, W.H.2
-
19
-
-
70349100958
-
-
Khronos Opencl Working Group version 1.0.29, December
-
Khronos OpenCL Working Group,. The OpenCL Specification, version 1.0.29, December 2008, http://khronos.org/registry/cl/specs/opencl-1.0.29.pdf
-
(2008)
The OpenCL Specification
-
-
-
21
-
-
79952016607
-
-
NVIDIA OpenCL Best Practices Guide, 2009, http://www.nvidia.com/content/ cudazone/CUDABrowser/downloads/papers/NVIDIAOpenCLBestPracticesGuide.pdf
-
(2009)
NVIDIA OpenCL Best Practices Guide
-
-
-
24
-
-
0003850954
-
-
2nd chapter 5 New York, NY, USA Prentice Hall
-
Rabaey J., Chandrakasan A., Nikolic B., Digital Integrated Circuits 2003 2nd chapter 5 New York, NY, USA Prentice Hall
-
(2003)
Digital Integrated Circuits
-
-
Rabaey, J.1
Chandrakasan, A.2
Nikolic, B.3
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