Bridging the GPGPU-FPGA efficiency gap

ACM/SIGDA International Symposium on Field Programmable Gate Arrays - FPGA

Volumn , Issue , 2011, Pages 119-122

  Fletcher, Christopher W ^a,b   Lebedev, Ilia A ^b   Asadi, Narges B ^c   Burke, Daniel R ^b   Wawrzynek, John ^b  

^a MASSACHUSETTS INSTITUTE OF TECHNOLOGY   (United States)

^b UNIVERSITY OF CALIFORNIA   (United States)

^c STANFORD UNIVERSITY   (United States)

Author keywords

Bayesian networks; FPGA; GPGPU; OpenCL; Reconfigurable computing

Indexed keywords

ARCHITECTURAL MODELS; BAYESIAN INFERENCE; CORE CLOCK; EXECUTION MODEL; FPGA; FPGA CORE; FPGA IMPLEMENTATIONS; GPGPU; HIGH LEVEL ARCHITECTURE; OPENCL; PROGRAMMABLE DEVICES; PROGRAMMING MODELS; RECONFIGURABLE COMPUTING; TEMPLATE-BASED;

BAYESIAN NETWORKS; DISTRIBUTED PARAMETER NETWORKS; INFERENCE ENGINES; INTELLIGENT NETWORKS; LOGIC GATES; PROGRAM PROCESSORS; RECONFIGURABLE HARDWARE;

FIELD PROGRAMMABLE GATE ARRAYS (FPGA);

EID: 79952909372     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1950413.1950439     Document Type: Conference Paper

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